Abstract is missing.
- Programmable/Stoppable Oscillator Based on Self-Timed RingsEslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin. 3-12 [doi]
- Design and Implementation of a GALS Adapter for ANoC Based ArchitecturesYvain Thonnart, Edith Beigné, Pascal Vivet. 13-22 [doi]
- A Programmable Adaptive Router for a GALS Parallel SystemJian Wu, Steve Furber, Jim D. Garside. 23-31 [doi]
- Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip LinksWilliam John Bainbridge, Sean James Salisbury. 35-44 [doi]
- The Lackey Self-Timed Switch-Fabric Design FrameworkScott Fairbanks. 45-54 [doi]
- A Delay-Insensitive Address-Event LinkJoseph Lin, Kwabena Boahen. 55-62 [doi]
- A Necessary and Sufficient Timing Assumption for Speed-Independent CircuitsSean Keller, Michael Katelman, Alain J. Martin. 65-76 [doi]
- Fault Tolerant Delay Insensitive Inter-chip CommunicationYebin Shi, Steve Furber, Jim D. Garside, Luis A. Plana. 77-84 [doi]
- GHz Asynchronous SRAM in 65nmJonathan Dama, Andrew Lines. 85-94 [doi]
- Synthesis of Multiple Rail Phase Encoding CircuitsAndrey Mokhov, Crescenzo D'Alessandro, Alex Yakovlev. 95-104 [doi]
- Modular Approach to Multi-resource Arbiter DesignStanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov, Alex Yakovlev. 107-116 [doi]
- Synchronizer Behavior and AnalysisIan W. Jones, Suwen Yang, Mark R. Greenstreet. 117-126 [doi]
- On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation SchemeGottfried Fuchs, Matthias Függer, Andreas Steininger. 127-136 [doi]
- Prime Indicants: A Synthesis Method for Indicating Combinational Logic BlocksWilliam B. Toms, Doug A. Edwards. 139-150 [doi]
- Characterization of Asynchronous Templates for Integration into Clocked CAD FlowsKenneth S. Stevens, Yang Xu, Vikas S. Vij. 151-161 [doi]
- Heuristic Based throughput Analysis and Optimization of Asynchronous PipelinesAlexander B. Smirnov, Alexander Taubin. 162-172 [doi]
- An Automatic Approach to Generate Haste Code from Simulink SpecificationsMaurizio Tranchero, Leonardo Maria Reyneri, Arjan Bink, Mark De Wit. 175-184 [doi]
- A Behavioral Synthesis Frontend to the Haste/TiDE Design FlowSune Fallgaard Nielsen, Jens Sparsø, Jonas Braband Jensen, Johan Sebastian Rosenkilde Nielsen. 185-194 [doi]
- Bottleneck Analysis and Alleviation in Pipelined Systems: A Fast Hierarchical ApproachGennette Gill, Montek Singh. 195-205 [doi]
- Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage TransistorsMasashi Imai, Kouei Takada, Takashi Nanya. 209-216 [doi]
- Reducing Power Consumption with Relaxed Quasi Delay-Insensitive CircuitsChristopher LaFrieda, Rajit Manohar. 217-226 [doi]