Abstract is missing.
- Taking Timing Out of the Equation: Moving Fully Automated Synthesis as close as possible to Delay-Insensitive CircuitsKarthi Srinivasan, Ole Richter, Jordan Schmerge, Rajit Manohar. 1-9 [doi]
- Generalized Binary Comparator Networks for QDI Combinational Logic SynthesisFlorian Huemer, Dylan Baumann. 10-18 [doi]
- Improved Logic Synthesis for Asynchronous CircuitsKarthi Srinivasan, Rajit Manohar. 19-27 [doi]
- A-ATPG: A Graph-based Automatic Test Pattern Generation Method for the DfT Architecture of Asynchronous Bundled-data CircuitsXuanyu Zhang, Jilin Zhang, Hong Chen. 28-35 [doi]
- A Test Architecture for Bundled-Data Asynchronous NoC Switches Using Commercial ATPG ToolsIordana Gaisidou, Giuseppe Chessa, Giannis Giannoulas, Artur Jutman, Davide Bertozzi, Christos P. Sotiriou. 36-44 [doi]
- Jumper: A State Capturing Element For Testability in Asynchronous Bundled-Data CircuitsIsmael de Almeida Junior, Azzadine Thajte, Cristiano Merio, Xavier Lesage, Adrien Godard, Ali Naimi, Sylvain Engels, Laurent Fesquet. 45-53 [doi]
- Automated FPGA-Based Wafer Testing of Asynchronous FlexICsMarcos L. L. Sartori, Yushu Qin, Shengyu Duan, Yujin Zheng, Rishad A. Shafik, Alex Yakovlev. 54-57 [doi]
- An Energy-Proportional, High-Speed Serial LinkAlex Huang, Amirmohammad Nazari, Robert Soulé, Rajit Manohar. 58-65 [doi]
- ANP-E: A 22-nm Asynchronous Spiking Recurrent Neural Network Processor Enabling On-chip Learning for Physiological Signal MonitoringYuan Hua, Chunqi Qian, Jilin Zhang, Hong Chen 0002. 66-73 [doi]
- Amplifier Circuit-Based Metastability ModelJürgen Burin, Afsah Anjum, Andreas Steininger. 74-82 [doi]
- Asymmetric Current-Starved Inverter Delay Lines for High-Performance Bundled-Data CircuitsJéssica Gonsalves Santos, Cristiano Merio, Adrien Godard, Ali Naimi, Sylvain Engels, Robin Wilson, Laurent Fesquet. 83-87 [doi]
- Effect of Self-Timed Design Styles on the Lifetime of NEMS CircuitsPhilipp Lehninger, Andreas Steininger, Axel Jantsch. 88-91 [doi]
- 74% Power Reduction in Bundled Data Circuits Thanks to Clock Gating IntegrationAdrien Godard, Robin Wilson, Sylvain Engels, Laurent Fesquet. 92-96 [doi]