Abstract is missing.
- A vision for embedded softwareAlberto L. Sangiovanni-Vincentelli, Grant Martin. 1-7 [doi]
- Establishing a tight bound on task interference in embedded system instruction cachesHarry Dwyer, John Fernando. 8-14 [doi]
- Heterogeneous memory management for embedded systemsOren Avissar, Rajeev Barua, Dave Stewart. 34-43 [doi]
- Transparent data-memory organizations for digital signal processorsSadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob. 44-48 [doi]
- A new method for compiling schizophrenic synchronous programsK. Schneider, M. Wenz. 49-58 [doi]
- An empirical evaluation of high level transformations for embedded processorsBjörn Franke, Michael F. P. O Boyle. 59-66 [doi]
- Combined partitioning and data padding for scheduling multiple loop nestsZhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu. 67-75 [doi]
- A novel approach to code analysis of digital signal processing systemsOlaf Lüthje, Martin Coors, Holger Keding. 76-83 [doi]
- The very portable optimizer for digital signal processorsSungjoon Jung, Yunheung Paek. 84-92 [doi]
- A software development tool chain for a reconfigurable processorAlberto La Rosa, Luciano Lavagno, Claudio Passerone. 93-98 [doi]
- Hardware compilation of sequential AdaMichael Ward, Neil C. Audsley. 99-107 [doi]
- Design space characterization for architecture/compiler co-explorationDirk Fischer, Jürgen Teich, Ralph Weper, Uwe Kastens, Michael Thies. 108-115 [doi]
- A compiler framework for mapping applications to a coarse-grained reconfigurable computer architectureGirish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm. 116-125 [doi]
- Efficient longest executable path search for programs with complex flows and pipeline effectsFriedhelm Stappert, Andreas Ermedahl, Jakob Engblom. 132-140 [doi]
- Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architecturesMarcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo. 141-148 [doi]
- A system-on-a-chip lock cache with task preemption supportBilge Saglam Akgul, Jaehwan Lee, Vincent John Mooney III. 149-157 [doi]
- ShiftQ: a bufferred interconnect for custom loop acceleratorsShail Aditya, Michael S. Schlansker. 158-167 [doi]
- Heads and tails: a variable-length instruction format supporting parallel fetch and decodeHeidi Pan, Krste Asanovic. 168-175 [doi]
- The emerging power crisis in embedded processors: what can a poor compiler do?Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John Mooney III, Krishna V. Palem, Kiran Puttaswamy, Weng-Fai Wong. 176-180 [doi]
- Application specific architectures: a recipe for fast, flexible and power efficient designsChristopher T. Weaver, Rajeev Krishna, Lisa Wu, Todd M. Austin. 181-185 [doi]
- Textiles and computing: background and opportunities for convergenceSungmee Park, Sundaresan Jayaraman. 186-187 [doi]
- A prototype network embedded in textile fabricKenneth Mackenzie, Eric Hudson, Drew Maule, Sundaresan Jayaraman, Sungmee Park. 188-194 [doi]
- Algorithms for energy optimization using processor instructionsAnil Seth, Ravindra B. Keskar, R. Venugopal. 195-202 [doi]
- The performance and energy consumption of three embedded real-time operating systemsKathleen Baynes, Chris Collins, Eric Fiterman, Brinda Ganesh, Paul Kohout, Christine Smit, Tiebing Zhang, Bruce L. Jacob. 203-210 [doi]
- Comparing power consumption of an SMT and a CMP DSP for mobile phone workloadsStefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu. 211-220 [doi]
- EDF scheduling using two-mode voltage-clock-scaling for hard real-time systemsYann-Hang Lee, Yoonmee Doh, C. Mani Krishna. 221-228 [doi]
- Energy-efficient instruction cache using page-based placementHyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 229-237 [doi]
- Computation offloading to save energy on handheld devices: a partition schemeZhiyuan Li, Cheng Wang, Rong Xu. 238-246 [doi]