Abstract is missing.
- R-tree: A Hardware ImplementationXiang Xiao, Tuo Shi, Pranav Vaidya, Jaehwan Lee. 3-9
- A Survey of Input Sensing and Processing Techniques for Multi-Touch SystemsJacob Pennock, M. Nasseh Tabrizi. 10-16
- CSPA: An Adder Faster Than Carry-LookaheadRanando King, Hai Jiang. 17-22
- Efficient Synthesis of Symmetric FunctionPijush Bhattacharjee. 23-29
- Improved Implementation Choices for Iterative Improvement Partitioning Algorithms on CircuitsYong-Hyuk Kim. 30-34
- Finding Minimal ESCT Expressions for Boolean Functions with Weight of up to 7Dimitrios Voudouris, Marinos Sampson, George K. Papakonstantinou. 35-41
- Design of Low-area Rijndael Hardware CoreYong-Sung Jeon, Sang-Woo Lee, Taek Yong Nam. 42-45
- Transcoding Load Distribution Policy for Wireless Mobile ClientsDongmahn Seo, Heonguil Lee, Inbum Jung. 46-52
- Security of QImage FileGabriela Mogos. 53-56
- Time-Domain Analysis of VLSI Interconnects Considering Oscillatory InputsRohit Sharma, Vivek Kumar Sehgal, Nitin Chanderwal, Saumya Rawat, Vinodini Kapoor, Sonia Chadha. 57-60
- Low Power Register File Design by Power Aware Register AssignmentWann-Yun Shieh, Shu-Yi Hsu. 63-69
- The Effect of Number of Virtual Channels on NoC EDPMahdieh Nadi Senjani, Mahdiar Hosein Ghadiry. 70-77
- Limits of Dynamic Voltage and Frequency Scaling AlgorithmsMahmoud Abdel-Fattah, Khaled El-Ayat. 78-84
- Effects of Register File Organization on Leakage Power ConsumptionPradeep Nair, Savithra Eratne, Eugene John. 85-88
- How to Really Save Computer Energy?Vasily G. Moshnyaga. 89-95
- A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel ArchitecturesGerd Pfeiffer, Manfred Schimmler. 99-104
- A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions for Multi-Output Incompletely Specified Boolean FunctionsMarinos Sampson, Dimitrios Voudouris, George K. Papakonstantinou. 105-111
- Scalable Directory Organization for Tiled CMP ArchitecturesAlberto Ros, Manuel E. Acacio, José M. García. 112-118
- A Novel Architecture for Fast Polynomial Division for Binary CoefficientsTarang Popat, Kaushal Buch. 119-123
- Embedding High-Performance Synchronous Routers to Asynchronous Network on ChipJeong-Gun Lee, Eun-Gu Jung. 124-128
- Nanocompilation for the Cell Matrix ArchitectureThomas Way, Rushikesh Katikar, Ch. Purushotham. 129-135
- Single-Electron Tunneling Circuits for Image Processing ApplicationsCosta Gerousis, David Ball. 139-144
- Modeling Non-Iterated System Behavior with Chu SpacesLubomir Ivanov. 145-150
- Low-Complexity Bypass Network Using Small RAMShinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita. 153-159
- A User-Space Device Driver FrameworkWilliam Grim, Stephen Blythe. 160-166
- A Multi-Block Interleaving Structure for NAND Flash Memory StorageJong-Min Jeong, Seung-Ho Park, Jung-Wook Park, Shin-Dug Kim, Charles C. Weems. 167-173
- Capturing Dynamic Memory StructuresMartin Uhl. 174-180
- High Performance CacheOscar Camacho Nieto, Luis A. Villa, Osvaldo Espinosa. 181-187
- Image Reconstruction Using Reconfigurable HardwareMuthana Hamd. 191-194
- Analysis & Modeling of Substrate Noise in Domino CMOS CircuitsSager Gosavi, Waleed K. Al-Assadi, Sasikiran Burugapalli. 195-200
- Subbus Control Line Impact on Effectiveness of Bus Encoding SchemesSrinivasa Vemuru, Ahmed Elkammar, Norman Scheinberg. 201-206
- A VHDL Design for PCAM. Hamd, Abdesselam Bouzerdoum. 207-210
- Nanowire Crossbar PLA with Adaptive Variable RedundancyMandar V. Joshi, Waleed K. Al-Assadi. 211-217
- High-Level Automatic Test Generation for VHDL DescriptionsFrançois Giamarchi, Laurent Capocchi, Dominique Federici, Paul Bisgambiglia. 218-223
- An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic CircuitsThanasin Bunnam, Arthit Thongtak. 224-228