Table of Contents

• Towards truly integrated photonic and electronic computingMoray McLaren. 1-2 [doi]
• Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scalingLingamneni Avinash, Kirthi Krishna Muntimadugu, Christian C. Enz, Richard M. Karp, Krishna V. Palem, Christian Piguet. 3-12 [doi]
• A reconfigurable optical/electrical interconnect architecture for large-scale clusters and datacentersDiego Lugones, Kostas Katrinis, Martin Collier. 13-22 [doi]
• BSArc: blacksmith streaming architecture for HPC acceleratorsMuhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé. 23-32 [doi]
• A limits study of benefits from nanostore-based future data-centric system architecturesJichuan Chang, Parthasarathy Ranganathan, Trevor N. Mudge, David Roberts, Mehul A. Shah, Kevin T. Lim. 33-42 [doi]
• Mesh independent loop fusion for unstructured mesh applicationsCarlo Bertolli, Adam Betts, Paul H. J. Kelly, Gihan R. Mudalige, Mike B. Giles. 43-52 [doi]
• GA-GPU: extending a library-based global address spaceprogramming model for scalable heterogeneouscomputing systemsVinod Tipparaju, Jeffrey S. Vetter. 53-64 [doi]
• SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detectionIsuru Herath, Demian Rosas-Ham, Mikel Luján, Ian Watson. 65-74 [doi]
• Architectural support of multiple hypervisors over single platform for enhancing cloud computing securityWeidong Shi, Jong Hyuk Lee, Taeweon Suh, Dong Hyuk Woo, Xinwen Zhang. 75-84 [doi]
• SuperCoP: a general, correct, and performance-efficient supervised memory systemBharghava Rajaram, Vijay Nagarajan, Andrew J. McPherson, Marcelo Cintra. 85-94 [doi]
• Exploring latency-power tradeoffs in deep nonvolatile memory hierarchiesDoe Hyun Yoon, Tobin Gonzalez, Parthasarathy Ranganathan, Robert S. Schreiber. 95-102 [doi]
• The tradeoffs of fused memory hierarchies in heterogeneous computing architecturesKyle Spafford, Jeremy S. Meredith, Seyong Lee, Dong Li, Philip C. Roth, Jeffrey S. Vetter. 103-112 [doi]
• DMA-circular: an enhanced high level programmable DMA controller for optimized management of on-chip local memoriesNikola Vujic, Lluc Alvarez, Marc González, Xavier Martorell, Eduard Ayguadé. 113-122 [doi]
• Studying the impact of application-level optimizations on the power consumption of multi-core architecturesShah Mohammad Faizur Rahman, Jichi Guo, Akshatha Bhat, Carlos Garcia, Majedul Haque Sujon, Qing Yi, Chunhua Liao, Daniel J. Quinlan. 123-132 [doi]
• Improving energy efficiency for mobile platforms by exploiting low-power sleep statesAlexander W. Min, Ren Wang, James Tsai, Mesut A. Ergin, Tsung-Yuan Charlie Tai. 133-142 [doi]
• Improving coherence protocol reactiveness by trading bandwidth for latencyLucia G. Menezo, Valentin Puente, Pablo Abad, José-Ángel Gregorio. 143-152 [doi]
• A programmable processing array architecture supporting dynamic task scheduling and module-level prefetchingJungHee Lee, Hyung Gyu Lee, Soonhoi Ha, Jongman Kim, Chrysostomos Nicopoulos. 153-162 [doi]
• Adaptive task duplication using on-line bottleneck detection for streaming applicationsYoonseo Choi, Cheng-Hong Li, Dilma Da Silva, Alan Bivens, Eugen Schenfeld. 163-172 [doi]
• Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architectureFrancesca Palumbo, Danilo Pani, Andrea Congiu, Luigi Raffo. 173-182 [doi]
• A hierachical configuration system for a massively parallel neural hardware platformFrancesco Galluppi, Sergio Davies, Alexander D. Rast, Thomas Sharp, Luis A. Plana, Steve Furber. 183-192 [doi]
• Reuse distance based performance modeling and workload mappingSai Prashanth Muralidhara, Mahmut T. Kandemir, Orhan Kislal. 193-202 [doi]
• The boat hull model: enabling performance prediction for parallel computing prior to code developmentCedric Nugteren, Henk Corporaal. 203-212 [doi]
• Parameterized micro-benchmarking: an auto-tuning approach for complex applicationsWenjing Ma, Sriram Krishnamoorthy, Gagan Agrawal. 213-222 [doi]
• A flexible OS-based approach for characterizing solid-state disk enduranceGokul B. Kandiraju, Kaoutar El Maghraoui. 223-232 [doi]
• An out-of-order vector processing mechanism for multimedia applicationsYe Gao, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 233-236 [doi]
• Towards player-driven procedural content generationNoor Shaker, Georgios N. Yannakakis, Julian Togelius. 237-240 [doi]
• An efficient vectorization of linked-cell particle simulationsWolfgang Eckhardt, Alexander Heinecke. 241-244 [doi]
• Dynamic percolation: a case of study on the shortcomings of traditional optimization in many-core architecturesElkin Garcia, Daniel A. Orozco, Rishi Khan, Ioannis E. Venetis, Kelly Livingston, Guang R. Gao. 245-248 [doi]
• CoreSymphony architectureTomoyuki Nagatsuka, Yoshito Sakaguchi, Kenji Kise. 249-252 [doi]
• Instructions activating conditions for hardware-based auto-schedulingSilvia Lovergine, Fabrizio Ferrandi. 253-256 [doi]
• Selective search of inlining vectors for program optimizationRosario Cammarota, Arun Kejariwal, Debora Donato, Alexandru Nicolau, Alexander V. Veidenbaum. 257-260 [doi]
• 3AS project: a different approach to the manycore challengesLorenzo Verdoscia, Roberto Vaccaro. 261-264 [doi]
• A capacity-efficient insertion policy for dynamic cache resizing mechanismsMasayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 265-268 [doi]
• Accelerated high-performance computing through efficient multi-process GPU resource sharingTeng Li, Vikram K. Narayana, Tarek A. El-Ghazawi. 269-272 [doi]
• Improving the performance of k-means clustering through computation skipping and data locality optimizationsOrhan Kislal, Piotr Berman, Mahmut T. Kandemir. 273-276 [doi]
• Learning, evolution and adaptation in racing gamesDaniele Loiacono. 277-284 [doi]
• Game AI revisitedGeorgios N. Yannakakis. 285-292 [doi]
• Towards more intelligent adaptive video game agents: a computational intelligence perspectiveSimon M. Lucas, Philipp Rohlfshagen, Diego Perez. 293-298 [doi]
• How AI can change the way we play gamesKenneth O. Stanley. 299-300 [doi]
• CRESTA: a software focussed approach to exascale co-designMark I. Parsons. 301-302 [doi]
• TERAFLUX: exploiting dataflow parallelism in teradevicesRoberto Giorgi. 303-304 [doi]
• DEEP: an exascale prototype architecture based on a flexible configurationArndt Bode. 305-306 [doi]
• Mont-Blanc: towards energy-efficient HPC systemsNikola Puzovic. 307-308 [doi]