Advances in Hardware Design and Verification, IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods, 16-18 October 1997, Montréal, Québec, Canada - researchr publication

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Hon F. Li, David K. Probst, editors, Advances in Hardware Design and Verification, IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods, 16-18 October 1997, Montréal, Québec, Canada. Volume 105 of IFIP Conference Proceedings, Chapman & Hall, 1997.

Conference: charme1997

Abstract is missing.

ASIC/system hardware verification at Nortel: a view from the trenchesAllan Silburt. 1

Proving the correctness of the interlock mechanism in processor designXiaoshan Li, Antonio Cau, Ben C. Moszkowski, Nick Coleman, Hussein Zedan. 5-22

Verifying out-of-order executionsWerner Damm, Amir Pnueli. 23-47

Formal modeling and validation applied to a commercial coherent bus: a case studyGanesh Gopalakrishnan, Rajnish Ghughal, Ravi Hosabettu, Abdelillah Mokkedem, Ratan Nalumasu. 48-62

An approach to Verilog-VHDL interoperability for synchronous designsDominique Borrione, F. Vestman, H. Bouamama. 65-87

A polymodal semantics for VHDLSubash Shankar, James R. Slagle. 88-105

A semantic model for VHDL-AMSNatividad Martínez Madrid, Peter T. Breuer, Carlos Delgado Kloos. 106-123

Model checking without hardware driversCarlos M. Roman, Gary De Palma, Robert P. Kurshan. 127

Efficient CTL* model checking for analysis of rainbow designsWillem Visser, Howard Barringer, Donal Fellows, Graham Gough, Alan Williams. 128-145

Symbolic model checking for a discrete clocked temporal logic with intervalsJürgen Ruf, Thomas Kropf. 146-163

A parallel approach to symbolic traversal based on set partitioningGianpiero Cabodi, Paolo Camurati, Antonio Lioy, Massimo Poncino, Stefano Quer. 167-184

Implementation of a multiple-domain decision diagram packageStefan Höreth. 185-202

Using induction and BDDs to model check invariantsDavid Déharbe, Anamaria Martins Moreira. 203-213

CheckOff-M: model checking and its role in IPRoger B. Hughes. 217

On the non-termination of MDGs-based abstract state enumerationOtmane Aït Mohamed, Xiaoyu Song, Eduard Cerny. 218-235

Simulation-based verification of network protocols performanceMario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero. 236-251

Integrated reasoning support in system design: design derivation and theorem provingSteven D. Johnson, Paul S. Miner. 255-272

Hardware compilation using attribute grammarsGeorge Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas. 273-290

Automatic post-synthesis verification support for a high level synthesis step by using the HOL theorem proving systemMatthias Mutz. 291-308

Is there a crisis in hardware verification?Carlos M. Roman. 309-310

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