Abstract is missing.
- Development of an optimizing compiler for a Fujitsu fixed-point digital signal processorSreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik. 2-6 [doi]
- Instruction set selection for ASIP designMichael Gschwind. 7-11 [doi]
- Resource constrained dataflow retiming heuristics for VLIW ASIPsMargarida F. Jacome, Gustavo de Veciana, Cagdas Akturan. 12-16 [doi]
- An ASIP design methodology for embedded systemsKayhan Küçükçakar. 17-21 [doi]
- Automatic detection of recurring operation patternsMarnix Arnold, Henk Corporaal. 22-26 [doi]
- A flexible code generation framework for the design of application specific programmable processorsFrançois Charot, Vincent Messé. 27-31 [doi]
- An MPEG-2 decoder case study as a driver for a system level design methodologyPieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees A. Vissers. 33-37 [doi]
- Timed executable system specification of an ADSL modem using a C++ based design environment: a case studyDirk Desmet, Michiel Esvelt, Prabhat Avasare, Diederik Verkest, Hugo De Man. 38-42 [doi]
- Flexible design of SPARC cores: a quantitative studyTomás Bautista, Antonio Núñez. 43-47 [doi]
- Hardware/software co-design of an avionics communication protocol interface system: an industrial case studyFrançois Clouté, Jean-Noël Contensou, Daniel Estève, Pascal Pampagnin, Philippe Pons, Yves Favard. 48-52 [doi]
- Multilanguage design of heterogeneous systemsPhilippe Coste, F. Hessel, P. LeMarrec, Zoltan Sugar, M. Romdhani, Rodolph Suescun, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya. 54-58 [doi]
- The case for a configure-and-execute paradigmFrank Vahid, Tony Givargis. 59-63 [doi]
- Designing digital video systems: modeling and schedulingH. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli. 64-68 [doi]
- Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuseFrançois Pogodalla, Richard Hersemeule, Pierre Coulomb. 69-73 [doi]
- Optimized rapid prototyping for real-time embedded heterogeneous multiprocessorsThierry Grandpierre, Christophe Lavarenne, Yves Sorel. 74-78 [doi]
- Using codesign techniques to support analog functionalityFrancis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou. 79-84 [doi]
- A compilation-based software estimation scheme for hardware/software co-simulationMarcello Lajolo, Mihai Lazarescu, Alberto L. Sangiovanni-Vincentelli. 85-89 [doi]
- A probabilistic performance metric for real-time system designTao Zhou, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha. 90-94 [doi]
- Iterative cache simulation of embedded CPUs with trace strippingZhao Wu, Wayne Wolf. 95-99 [doi]
- Optimizing geographically distributed timed cosimulation by hierarchically grouped messagesSungjoo Yoo, Kiyoung Choi. 100-104 [doi]
- Peer-based multithreaded executable co-specificationDonald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber. 105-109 [doi]
- Timing coverification of concurrent embedded real-time systemsPao-Ann Hsiung. 110-114 [doi]
- Worst-case analysis of discrete systems based on conditional abstractionsFelice Balarin. 115-119 [doi]
- A unified formal model of ISA and FSMDJianwen Zhu, Daniel Gajski. 121-125 [doi]
- Co-design tool construction using APICESAnsgar Bredenfeld. 126-130 [doi]
- Graph based communication analysis for hardware/software codesignPeter Voigt Knudsen, Jan Madsen. 131-135 [doi]
- System synthesis utilizing a layered functional modelIngo Sander, Axel Jantsch. 136-140 [doi]
- Communication refinement in video systems on chipJean-Yves Brunel, Erwin A. de Kock, W. M. Kruijtzer, H. J. H. N. Kenter, W. J. M. Smits. 142-146 [doi]
- Compiling Esterel into sequential codeStephen A. Edwards. 147-151 [doi]
- Power estimation for architectural exploration of HW/SW communication on system-level busesWilliam Fornaciari, Donatella Sciuto, Cristina Silvano. 152-156 [doi]
- Software controlled power managementYung-Hsiang Lu, Tajana Simunic, Giovanni De Micheli. 157-161 [doi]
- A statechart based HW/SW codesign systemI. D. Bates, E. Graeme Chester, D. J. Kinniment. 162-166 [doi]
- 3D exploration of software schedules for DSP algorithmsJürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya. 168-172 [doi]
- Scheduling hardware/software systems using symbolic techniquesKarsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich. 173-177 [doi]
- Scheduling with optimized communication for time-triggered embedded systemsPaul Pop, Petru Eles, Zebo Peng. 178-182 [doi]
- A hardware-software cosynthesis technique based on heterogeneous multiprocessor schedulingHyunok Oh, Soonhoi Ha. 183-187 [doi]
- Embedded system synthesis under memory constraintsJan Madsen, Peter Bjørn-Jørgensen. 188-192 [doi]
- Overhead effects in real-time preemptive schedulesDavid L. Rhodes, Wayne Wolf. 193-197 [doi]
- System-level partitioning with uncertaintyJones Albuquerque, Claudionor José Nunes Coelho Jr., Carlos Frederico Cavalcanti, Diógenes Cecilio da Silva Jr., Antônio Otávio Fernandes. 198-202 [doi]
- Timing-driven HW/SW codesign based on task structuring and process timing simulationDinesh Ramanathan, Ali Dasdan, Rajesh K. Gupta. 203-207 [doi]
- Aspects of system-level designJonas Plantin, Erik Stoy. 209-210 [doi]
- How standards will enable hardware/software co-designMark Genoe, Christopher K. Lennard, Joachim Kunkel, Brian Bailey, Gjalt G. de Jong, Grant Martin, M. M. Kamal Hashmi, Shay Ben-Chorin, Anssi Haverinen. 211-212 [doi]