Abstract is missing.
- CODES and co-design: a look back and a look forwardWayne Wolf. 2 [doi]
- The usage of stochastic processes in embedded system specificationsAxel Jantsch, Ingo Sander, Wenbiao Wu. 5-10 [doi]
- Modeling and evaluation of hardware/software designsNeal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas. 11-16 [doi]
- SystemC: a homogenous environment to test embedded systemsAlessandro Fin, Franco Fummi, Maurizio Martignano, Mirko Signoretto. 17-22 [doi]
- Embedded UML: a merger of real-time UML and co-designGrant Martin, Luciano Lavagno, Jean Louis-Guerin. 23-28 [doi]
- Hardware/software partitioning of embedded system in OCAPI-xlGeert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Ivo Bolsens. 30-35 [doi]
- HW/SW partitioning of an embedded instruction memory decompressorShlomo Weiss, Shay Beren. 36-41 [doi]
- MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphsKaram S. Chatha, Ranga Vemuri. 42-47 [doi]
- A practical tool box for system level communication synthesisDenis Hommais, Frédéric Pétrot, Ivan Augé. 48-53 [doi]
- System canvas: a new design environment for embedded DSP and telecommunication systemsPraveen K. Murthy, Etan G. Cohen, Steve Rowland. 54-59 [doi]
- Designing domain-specific processorsMarnix Arnold, Henk Corporaal. 61-66 [doi]
- RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processorsCagdas Akturan, Margarida F. Jacome. 67-72 [doi]
- A novel parallel deadlock detection algorithm and architecturePun H. Shiu, Yudong Tan, Vincent John Mooney III. 73-78 [doi]
- Towards effective embedded processors in codesigns: customizable partitioned cachesPeter Petrov, Alex Orailoglu. 79-84 [doi]
- Development cost and size estimation starting from high-level specificationsWilliam Fornaciari, Fabio Salice, Umberto Bondi, Edi Magini. 86-91 [doi]
- Exploring design space of parallel realizations: MPEG-2 decoder case studyBasant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan. 92-97 [doi]
- Source-level execution time estimation of C programsCarlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto. 98-103 [doi]
- STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systemsFelice Balarin. 104-108 [doi]
- Evaluating register file size in ASIP designManoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan. 109-114 [doi]
- Generating mixing hardware/software systems from SDL specificationsFrank Slomka, Matthias Dörfel, Ralf Münzenberger. 116-121 [doi]
- Area-efficient buffer binding based on a novel two-port FIFO structureKyoungseok Rha, Kiyoung Choi. 122-127 [doi]
- Deriving hard real-time embedded systems implementations directly from SDL specificationsJosé M. Álvarez, Manuel Díaz, Luis Llopis, Ernesto Pimentel, José M. Troya. 128-133 [doi]
- A trace transformation technique for communication refinementPaul Lieverse, Pieter van der Wolf, Ed F. Deprettere. 134-139 [doi]
- A systematic approach to software peripherals for embedded systemsDimitris Lioupis, Apostolos Papagiannis, Dionysia Psihogiou. 140-145 [doi]
- A constructive algorithm for memory-aware task assignment and schedulingRadoslaw Szymanek, Krzysztof Kuchcinski. 147-152 [doi]
- A constraint-based application model and scheduling techniques for power-aware systemsJinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi. 153-158 [doi]
- Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systemsSid Ahmed Ali Touati. 159-164 [doi]
- Scheduling-based code size reduction in processors with indirect addressing modeSungtaek Lim, Jihong Kim, Kiyoung Choi. 165-169 [doi]
- Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platformChun Wong, Paul Marchal, Peng Yang. 170-177 [doi]
- Parameterised system design based on genetic algorithmsGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi. 177-182 [doi]
- Minimizing system modification in an incremental design approachPaul Pop, Petru Eles, Traian Pop, Zebo Peng. 183-188 [doi]
- High-level architectural co-simulation using Esterel and CAndré Chátelain, Yves Mathys, Giovanni Placido, Alberto La Rosa, Luciano Lavagno. 189-194 [doi]
- A generic wrapper architecture for multi-processor SoC cosimulation and designSungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya. 195-200 [doi]
- The TACO protocol processor simulation environmentSeppo Virtanen, Johan Lilius. 201-206 [doi]
- Formal synthesis and code generation of embedded real-time softwarePao-Ann Hsiung. 208-213 [doi]
- Whole program compilation for embedded software: the ADSL experimentJohan Cockx. 214-218 [doi]
- Compiler-directed selection of dynamic memory layoutsMahmut T. Kandemir, Ismail Kadayif. 219-224 [doi]
- Logic optimization and code generation for embedded control applicationsYunjian Jiang, Robert K. Brayton. 225-229 [doi]
- Empirical comparison of software-based error detection and correction techniques for embedded systemsRoyan H. L. Ong, Michael J. Pont. 230-235 [doi]
- Dynamic I/O power management for hard real-time systemsVishnu Swaminathan, Krishnendu Chakrabarty, S. Sitharama Iyengar. 237-242 [doi]
- Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessorsNeal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler. 243-248 [doi]
- Processor frequency setting for energy minimization of streaming multimedia applicationAndrea Acquaviva, Luca Benini, Bruno Riccò. 249-253 [doi]
- Retargetable compilation for low powerWen-Tsong Shiue. 254-259 [doi]
- A design framework to efficiently explore energy-delay tradeoffsWilliam Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria. 260-265 [doi]