Abstract is missing.
- Message from the Organizing Committee ChairHiroaki Kobayashi. [doi]
- Message from the Program Committee ChairsMakoto Ikeda, Fumio Arakawa. [doi]
- Message from the Advisory Committee ChairTadao Nakamura. [doi]
- Keynote & invited speaker's biography [7 biographies]Bert Gyselinckx, Hiroshi Kanayama, Michael McCool, Shintaro Momose, Takeshi Kataoka, James Myers, Toshio Yoshida. [doi]
- HW/SW approaches to accelerate GRAPES in an FU arrayWei Wang, Jun Yao, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, Weimin Zheng. 1-3 [doi]
- Automatic parallelization, performance predictability and power control for mobile-applicationsDominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara. 1-3 [doi]
- A multi-granularity parallelism object recognition processor with content-aware fine-grained task schedulingJunyoung Park, Injoon Hong, Gyeonghoon Kim, Youchang Kim, Kyuho Jason Lee, Seongwook Park, Kyeongryeol Bong, Hoi-Jun Yoo. 1-3 [doi]
- Panel discussions the next step in processor evolutionYoshio Masubuchi, Bert Gyselinckx, Michael McCool, Shintaro Momose, James Myers, Toshio Yoshida. 1-2 [doi]
- Hardware support for resource partitioning in real-time embedded systemsTetsuro Honmura, Yuki Kondo, Tetsuya Yamada, Masashi Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama, Yasuhiko Saitoh, Hirofumi Nishi, Mikiko Sato, Mitaro Namiki. 1-3 [doi]
- Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessorsKazuhisa Ishizaka, T. Miyamoto, S. Akimoto, A. Iketani, T. Hosomi, Junji Sakai. 1-3 [doi]
- A flexible insertion policy for dynamic cache resizing mechanismsMasayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 1-3 [doi]
- Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compilerYohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara. 1-3 [doi]
- Dynamic power on/off method for 3D NoCs with wireless inductive-coupling linksHao Zhang 0020, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. 1-3 [doi]
- Architecture level TSV count minimization methodology for 3D tree-based FPGAVinod Pangracious, Habib Mehrez, Zied Marrakchi. 1-3 [doi]
- RXv2 processor core for low-power microcontrollersSugako Otani, Naoshi Ishikawa, Hiroyuki Kondo. 1-3 [doi]
- Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistorHidetomo Kobayashi, Kiyoshi Kato, Takuro Ohmaru, Seiichi Yoneda, Tatsuji Nishijima, Shuhei Maeda, Kazuaki Ohshima, Hikaru Tamura, Hiroyuki Tomatsu, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Jun Koyama, Shunpei Yamazaki. 1-3 [doi]
- A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interfaceNoriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura. 1-3 [doi]