Abstract is missing.
- A min-cut placement algorithm for general cell assemblies based on a graph representationUlrich Lauther. 1-10 [doi]
- A two-dimensional placement algorithm for the master slice LSI layout problemSatoshi Goto. 11-17 [doi]
- A hierarchical placement procedure with a simple blocking schemeShinichi Murai, Hiroo Tsuji, Morio Kakinuma, Kazumichi Sakaguchi, Chiyoji Tanaka. 18-23 [doi]
- Placement algorithm by partitioning for optimum rectangular placementEdward P. Stabler, Victor M. Kureichik, Valery A. Kalashnikov. 24-25 [doi]
- Incremental processing applied to Steinberg's placement procedureHarold W. Carter, Melvin A. Breuer, Zahir A. Syed. 26-31 [doi]
- The use of color and 3-D temporal and spatial data management techniques in computer-aided designWayne E. Carlson, Richard E. Parent, Charles Csuri. 32-38 [doi]
- A low cost satellite for fast interactive graphics in a time-sharing environmentB. Meyer. 39-44 [doi]
- Concepts of a microcomputer design languageYaohan Chu. 45-52 [doi]
- The MIMOLA design system a computer aided digital processor design methodGerhard Zimmermann. 53-58 [doi]
- The MIMOLA design system: Detailed description of the software systemPeter Marwedel. 59-63 [doi]
- Instruction set processor specifications for simulation, evaluation, and synthesisMario Barbacci. 64-72 [doi]
- The CMU design automation system: An example of automated data path designAlice C. Parker, Donald E. Thomas, Daniel P. Siewiorek, Mario Barbacci, Louis J. Hafer, G. W. Leive, Jinchoon Kim. 73-80 [doi]
- Unified Shapes Checker - a checking tool for LSICarl R. McCaw. 81-87 [doi]
- Circuit simulation and timing verification based on MOS/LSI mask informationToshiro Akino, Masafumi Shimode, Yukinaga Kurashige, Toshio Negishi. 88-94 [doi]
- LSI layout checking using bipolar device recognition techniqueC. S. Chang. 95-101 [doi]
- CALMOS: A portable software system for the automatic and interactive layout of MOS/LSIHerman Beke, Willy Sansen. 102-108 [doi]
- A new circuit placement program for FET chipsK. W. Lallier, R. K. Jackson. 109-113 [doi]
- An experimental input system of hand-drawn logic circuit diagram for LSI CADMitsuo Ishii, Masanari Yamamoto, Michiko Iwasaki, Hiroshi Shiraishi. 114-120 [doi]
- Automatic pipe routing and material take-off system for chemical plantYoshio Matsui, Hironori Takagi, Shigekazu Emori, Norio Masuda, Shohei Sasabe, Chuzo Yoshimura, Toshikazu Shirai, Susumu Nioh, Bunzi Kinno. 121-127 [doi]
- Stonewalls: Experiments in intelligent draftingChris I. Yessios. 128-134 [doi]
- DRAW3D: Time sharing graphic interaction using a device-space bufferNicholas H. Weingarten, William Kovacs, Michael Corden. 135-141 [doi]
- Computer simulation of foliage shading in building energy loadsMarc Schiler, Donald P. Greenberg. 142-148 [doi]
- Multiple fault diagnosis in combinational networksCharles W. Cha. 149-155 [doi]
- TMEAS, a testability measurement programJohn Grason. 156-161 [doi]
- Testing of MOS combinational networks a procedure for efficient fault simulation and test generationYacoub M. El-Ziq. 162-170 [doi]
- Behavioral-level test developmentWilliam A. Johnson. 171-179 [doi]
- Generation of hazard free tests using the D-algorithm in a timing accurate system for logic and deductive fault simulationEskil Kjelkerud, Owe Thessén. 180-184 [doi]
- Designers Workbench - efficient and economical design aidsLawrence A. O'Neill, C. G. Savolaine, T. J. Thompson, Jeffery M. Franke, Robert A. Friedenson, E. D. Walsh, P. H. McDonald, J. R. Breiland, D. S. Evans. 185-199 [doi]
- A procedure for checking the topological consistency of a 2-D or 3-D finite element meshKenneth Preiss. 200-206 [doi]
- Computer Aided Ship Design and numerically controlled production of towing tank modelsDavid F. Rogers, Francisco Rodriguez, Steven G. Satterfield. 207-214 [doi]
- Automation of manufacturing planning, shop loading and work measurement in an engineering job shop environmentEdward J. Bresnen. 215-221 [doi]
- A partial solution to fitting large parametric surfaces in computer-aided design systemsLarry Lichten. 222-228 [doi]
- Macrosimulation with Quasi-general Symbolic FET Macromodel and Functional LatencyH. Y. Hsieh, N. B. Rabbat. 229-234 [doi]
- Methods of modelling digital devices for logic simulationEskil Kjelkerud, Owe Thessén. 235-241 [doi]
- Digital logic simulation at the gate and functional levelPhilip S. Wilcox. 242-248 [doi]
- A hybrid scheduling technique for hierarchical logic simulators or "Close Encounters of the Simulated Kind"Will Sherwood. 249-254 [doi]
- Efficient simulation of AHPLZainalabedin Navabi, Fredrick J. Hill. 255-262 [doi]
- SILOG: A practical tool for large digital network simulationNorbert Giambiasi, A. Miara, D. Muriach. 263-271 [doi]
- SABLE: A tool for generating structured, multi-level simulationsDwight D. Hill, William M. van Cleemput. 272-279 [doi]
- Symbolic simulation for correct machine designWilliam C. Carter, William H. Joyner Jr., Daniel Brand. 280-286 [doi]
- Optimal layout of CMOS functional arraysTakao Uehara, William M. van Cleemput. 287-289 [doi]
- The minimum width routing of A 2-row 2-layer polycell-layoutTatsuya Kawamoto, Yoji Kajitani. 290-296 [doi]
- MIRAGE - a simple-model routing program for the hierarchical layout design of IC masksKoji Sato, Takao Nagai, Hiroyoshi Shimoyama, Toshihiko Yahara. 297-304 [doi]
- Introduction to silicon compilationJohn P. Gray. 305-306 [doi]
- IC specification languageRon Ayres. 307-309 [doi]
- Bristle Blocks: A silicon compilerDave Johannsen. 310-313 [doi]
- Silicon compilation-a hierarchical use of PLAsRon Ayres. 314-326 [doi]
- A software system for Automated Placement And Wiring of LSI chipsPao-Tsin Wang, Paul Bassett. 327-329 [doi]
- Dynamic design rule checking in an interactive printed circuit editorTom C. Bennett, Kim R. Stevens, William M. van Cleemput. 330-336 [doi]
- PC board layout techniquesDavid R. Johnson. 337-343 [doi]
- The real world of design automation - part II or adapting to the joys of madness (Panel Session)P. H. McDonald. 344-345 [doi]
- "Views of a vendor" (Position Paper)Michael J. Cronin. 346 [doi]
- Design Automation concerns (Position Paper)J. B. Kane. 347-348 [doi]
- Future of design automation (Position Paper)Paul Losleben. 349 [doi]
- Moving a D.A. system from development to production (Position Paper)Waldo George Magnuson Jr.. 350-351 [doi]
- Design Automation philosophies (Position Paper)Donald L. Peterson. 352 [doi]
- Design verification based on functional abstractionSany M. Leinwand, T. Lamdan. 353-359 [doi]
- Design and verification of large-scale computers by using DDLNobuaki Kawato, Takao Saito, Fumihiro Maruyama, Takao Uehara. 360-366 [doi]
- Logic verification system for very large computers using LSI'sYasuhiro Ohno, Masayuki Miyoshi, Katsuya Sato. 367-374 [doi]
- The application of program verification techniques to hardware verificationJohn A. Darringer. 375-381 [doi]
- Cost effective data entry techniques for design automationJerry T. Harvel. 382 [doi]
- Electron beam lithographyFaik S. Ozdemir. 383-391 [doi]
- Hughes S&CG custom LSI layouts - 'we did it our way'R. R. Rath. 392-397 [doi]
- A Computer-Aided Design data baseStanley Wong, W. A. Bristol. 398-402 [doi]
- Hierarchical modeling and simulation in VISTARobert I. Gardner, Paul B. Weil. 403-405 [doi]
- A placement capability based on partitioningLorretta I. Corrigan. 406-413 [doi]
- A design aids data base for digital componentsDaniel J. Sucher, Donald F. Wann. 414-420 [doi]
- Descriptive databases in some design/manufacturing environmentsEdward Marlow Hoskins. 421-436 [doi]
- Component library for an integratel DA systemKuo-Yen Nieng, Dennis A. Beckley. 437-444 [doi]
- The design of an efficient data base to support an interactive LSI layout systemJames A. Wilmore. 445-451 [doi]
- The complete VLSI design systemM. F. Oakes. 452-460 [doi]
- Topological analysis for VLSI circuitsPaul Losleben, Kathryn Thompson. 461-473 [doi]
- Placement algorithms for arbitrarily shaped blocksBryan Preas, William M. van Cleemput. 474-480 [doi]
- Global routerJirí Soukup. 481-484 [doi]
- New algorithms for grid-less routing of high density printed circuit boardsS. Pimont. 485 [doi]
- A "lookahead" router for multilayer printed wiring boardsJohn C. Foster. 486-493 [doi]
- An application of branch and bound method to automatic printed circuit board routingLawrence Dysart, Mikhail Koifman. 494-499 [doi]
- An interactive routing program with On-line clean-up of sketched routesOla A. Marvik. 500-505 [doi]
- An interactive layout system of analog printed wiring boardsKen-ichi Sahara, Ken-ichi Kobori, Ikuo Nishioka. 506-512 [doi]
- An introduction to the N. mPc design environmentFrederic I. Parke. 513-519 [doi]
- The N. mPc system description facilityCharles W. Rose, Larry A. Rogers, Ralph Straubs. 520-528 [doi]
- The N.mPc runtime environmentFrederic I. Parke, Donald C. Hewitt Jr., Charles W. Rose. 529-536 [doi]
- An evaluation of the N. mPc design environmentGregory M. Ordy, Frederic I. Parke. 537-542 [doi]
- Can C.A.D. meet the VLSI design problems of the 80's?(Panel Discussion)David Gibson. 543 [doi]
- Will Disign tools catch up to VLSI designDavid Giuliani. 544-545 [doi]
- VLSI - a design challengeRonald Waxman. 546-547 [doi]
- VLSI design methodology the problem of the 80's for microprocessor designBill Lattin. 548-549 [doi]
- CAD system for VLSIWarren Wiemann. 550 [doi]
- Can CAD meet the VLSI design problems of the 80's?Robert P. Larsen. 551 [doi]
- Can CAD meet the VLSI design problems of the 80'sDavid W. Hightower. 552-553 [doi]
- Computer hardware description languages and their applicationsWilliam M. van Cleemput. 554-560 [doi]
- Developments in computer simulation of gate level physical logicLionel Bening. 561-567 [doi]