Abstract is missing.
- DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead InterconnectAbhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy. 1-8 [doi]
- High Performance Instruction Scheduling Circuits for Out-of-Order Soft ProcessorsHenry Wong, Vaughn Betz, Jonathan Rose. 9-16 [doi]
- GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator AcceleratorJan Gray. 17-20 [doi]
- Tinker: Generating Custom Memory Architectures for Altera's OpenCL CompilerDustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner. 21-24 [doi]
- Evaluating Embedded FPGA Accelerators for Deep Learning ApplicationsGopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Vamsi Buddha, Nachiket Kapre. 25 [doi]
- Communication Optimization for the 16-Core Epiphany Floating-Point Processor ArrayNachiket Kapre, Siddhartha. 26 [doi]
- A LUT-Based Approximate AdderAndreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich. 27 [doi]
- Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing PlatformsErnst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars. 28 [doi]
- When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing AccelerationYu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei. 29 [doi]
- Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal?Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav G. Sedukhin. 30 [doi]
- RP-Ring: A Heterogeneous Multi-FPGA Accelerating Solution for N-Body SimulationsTianqi Wang, Xi Jin, Bo Peng, Chuanjun Wang, Linlin Zheng. 31 [doi]
- The SMEM Seeding Acceleration for DNA Sequence AlignmentMau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu. 32-39 [doi]
- fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAsStylianos I. Venieris, Christos-Savvas Bouganis. 40-47 [doi]
- Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using DropoutJiang Su, David B. Thomas, Peter Y. K. Cheung. 48-51 [doi]
- Two-Hit Filter Synthesis for Genomic Database SearchJordan A. Bradshaw, Rasha Karakchi, Jason D. Bakos. 52-55 [doi]
- KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA DesignsEddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides. 56-63 [doi]
- SynADT: Dynamic Data Structures in High Level SynthesisZeping Xue, David B. Thomas. 64-71 [doi]
- Loop Splitting for Efficient Pipelining in High-Level SynthesisJunyi Liu, John Wickerson, George A. Constantinides. 72-79 [doi]
- Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing ClosureQue Yanghua, Nachiket Kapre, Harnhua Ng, Kirvy Teo. 80-83 [doi]
- Knowledge Transfer in Automatic Optimisation of Reconfigurable DesignsMaciej Kurek, Marc Peter Deisenroth, Wayne Luk, Timothy John Todman. 84-87 [doi]
- Reconfiguration Control Networks for TMR Systems with Module-Based RecoveryDimitris Agiakatsikas, Nguyen T. H. Nguyen, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong. 88-91 [doi]
- Vertex-Centric Graph Processing on FPGANina Engelhardt, Hayden Kwok-Hay So. 92 [doi]
- High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round TwoWilliam Diehl, Kris Gaj. 93 [doi]
- Accelerating Apache Spark Big Data Analysis with FPGAsEhsan Ghasemi, Paul Chow. 94 [doi]
- Parallel Hardware Merge SorterWei Song, Dirk Koch, Mikel Luján, Jim D. Garside. 95-102 [doi]
- High-Throughput and Energy-Efficient Graph Processing on FPGAShijie Zhou, Charalampos Chelmis, Viktor K. Prasanna. 103-110 [doi]
- Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon. 111-118 [doi]
- Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGADana L. How, Sean Atsatt. 119-126 [doi]
- AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLSLiwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow. 127-130 [doi]
- Cost Effective Partial Scan for Hardware EmulationTao Li, Qiang Liu. 131-134 [doi]
- Initiation Interval Aware Resource Sharing for FPGA DSP BlocksBajaj Ronak, Suhaib A. Fahmy. 135 [doi]
- A Dynamically Scheduled Architecture for the Synthesis of Graph Database QueriesMarco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi, Marco Lattuada. 136 [doi]
- Acceleration of the Pair-HMM Algorithm for DNA Variant CallingGowthami Jayashri Manikandan, Sitao Huang, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen. 137 [doi]
- An Empirical Analysis of the Fidelity of VPR Area ModelsFarheen Fatima Khan, Andy Ye. 138 [doi]
- Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoCAmine Ait Si Ali, Xiaojun Zhai, Abbes Amira, Faycal Bensaali, Naeem Ramzan. 139 [doi]
- A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMsAmeer M. S. Abdelhadi, Guy G. F. Lemieux. 140-147 [doi]
- P4-to-VHDL: Automatic Generation of 100 Gbps Packet ParsersPavel Benácek, Viktor Pus, Hana Kubatova. 148-155 [doi]
- Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCsNachiket Kapre. 156-163 [doi]
- Parallelizing FPGA Technology Mapping through PartitioningChuyu Shen, Zili Lin, Ping Fan, Xianglong Meng, Weikang Qian. 164-167 [doi]
- Online Bandwidth Reduction Using Dynamic Partial ReconfigurationSeyyed Mahdi Najmabadi, Zhe Wang, Yousef Baroud, Sven Simon. 168-171 [doi]
- Energy Efficiency of Full Pipelining: A Case Study for Matrix MultiplicationPeipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, André DeHon. 172-175 [doi]
- Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable HardwareDajung Lee, Roger Moussalli, Sameh W. Asaad, Mudhakar Srivatsa. 176-183 [doi]
- A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC EnvironmentTanja Harbaum, Mahmoud Seboui, Matthias Balzer, Jürgen Becker, Marc Weber. 184-191 [doi]
- FPGA-Accelerated Particle-Grid MappingAhmed Sanaullah, Arash Khoshparvar, Martin C. Herbordt. 192-195 [doi]
- Finding Space-Time Stream Permutations for Minimum Memory and LatencyThaddeus Koehn, Peter M. Athanas. 196 [doi]
- Application-Aware Collective Communication (Extended Abstract)Jiayi Sheng, Qingqing Xiong, Chen Yang, Martin C. Herbordt. 197 [doi]
- Bridging the Performance-Programmability Gap for FPGAs via OpenCL: A Case Study with OpenDwarfsKonstantinos Krommydas, Ahmed E. Helal, Anshuman Verma, Wu-chun Feng. 198 [doi]
- ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic CoolingZhiyuan Yang, Caleb Serafy, Ankur Srivastava. 199 [doi]
- FPGA-Based Reduction Techniques for Efficient Deep Neural Network DeploymentAdam Page, Tinoosh Mohsenin. 200 [doi]
- CS-Based Secured Big Data Processing on FPGAAmey M. Kulkarni, Ali Jafari, Colin Shea, Tinoosh Mohsenin. 201 [doi]
- High Level Synthesis Based E-Nose System for Gas ApplicationsAmine Ait Si Ali, Abbes Amira, Faycal Bensaali, Mohieddine Benammar, Muhammad Hassan, Amine Bermak. 202-203 [doi]
- Runtime Parameterizable Regular Expression Operators for DatabasesZsolt István, David Sidler, Gustavo Alonso. 204-211 [doi]
- Accelerating Equi-Join on a CPU-FPGA Heterogeneous PlatformRen Chen, Viktor K. Prasanna. 212-219 [doi]