Abstract is missing.
- FPGA-Based Database Query Processing on Arbitrarily Wide TablesMehdi Moghaddamfar, Christian Färber, Norman May, Wolfgang Lehner, Akash Kumar 0001. 1 [doi]
- MaNaBIT: A Versatile Tool for Manipulating and Analyzing FPGA BitstreamsNajdet Charaf, Christoph Tietz, Diana Goehringer. 1 [doi]
- An Evaluation of Using CCIX for Cache-Coherent Host-FPGA InterfacingSajjad Tamimi, Florian Stock, Andreas K. Maier, Arthur Bernhardt, Ilia Petrov 0001. 1-9 [doi]
- Dynamic C-Slow Pipelining for HLSJianyi Cheng, John Wickerson, George A. Constantinides. 1-10 [doi]
- A Near-Memory Radix Sort Accelerator with Parallel 1-bit SorterJihwan Cho, Dalta Imam Maulana, Wanyeong Jung. 1 [doi]
- FPGA-assisted Massive Packet Queueing and Traffic Shaping at the Network EdgeRalf Kundel, Leonhard Nobach, Hans-Joerg Kolbe, Tobias Meuser, Ralf Steinmetz. 1 [doi]
- Reverse Engineering Neural Network Folding with Remote FPGA Power AnalysisVincent Meyers, Dennis Gnad, Mehdi B. Tahoori. 1-10 [doi]
- Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nmSajjad Rostami-Sani, Anas Razzaq, Andy Ye. 1-9 [doi]
- A Generator of Numerically-Tailored and High-Throughput Accelerators for Batched GEMMsLouis Ledoux, Marc Casas. 1-10 [doi]
- Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo SchedulingNicolai Fiege, Patrick Sittel, Peter Zipf. 1-2 [doi]
- Dual-Line-Systolic Array for High Performance CNN AcceleratorPeng Xue, Lunshuai Pan, Litao Sun, Mingqiang Huang. 1 [doi]
- An FPGA Accelerator for Genome Variant CallingTiancheng Xu, Scott Rixner, Alan L. Cox. 1-9 [doi]
- CoMeFa: Compute-in-Memory Blocks for FPGAsAman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus Hanindhito, Jaydeep Kulkarni, Lizy K. John. 1-9 [doi]
- An Efficient FPGA Implementation of k-Nearest Neighbors via Online ArithmeticSaeid Gorgin 0001, MohammadHosein Gholamrezaei, Danial Javaheri, Jeong-A Lee. 1-2 [doi]
- A Virtual Machine Approach for High-level FPGA ProgrammingLoïc Sylvestre, Jocelyn Sérot, Emmanuel Chailloux. 1 [doi]
- FCsN: A FPGA-Centric SmartNIC Framework for Neural NetworksAnqi Guo, Tong Geng, Yongan Zhang, Pouya Haghi, Chunshu Wu, Cheng Tan 0002, Yingyan Lin, Ang Li, Martin C. Herbordt. 1-2 [doi]
- Low-Latency Modular Exponentiation for FPGAsMartin Langhammer, Sergey Gribok, Bogdan Pasca. 1-9 [doi]
- Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAsXiang Li, Russell Tessier, Daniel E. Holcomb. 1-5 [doi]
- Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based AcceleratorsRuiqi Chen, Yuhanxiao Ma, Shaodong Zheng, Shizhen Huang, Chao Chen, Jun Yu, Kun Wang. 1 [doi]
- Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-WorkTong Wu, Oliver Diessel. 1-5 [doi]
- A High-Performance Hardware Architecture for ECC Point Multiplication over Curve25519Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Xin Long, Yuan Zhao, Yinchao Zou. 1-9 [doi]
- Resource Sharing in Dataflow CircuitsLana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne. 1-9 [doi]
- OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Multi-Die FPGAsGyeongcheol Shin, Junsoo Kim, Joo-Young Kim. 1 [doi]
- NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse EngineeringYukui Luo, Shijin Duan, Cheng Gongye, Yunsi Fei, Xiaolin Xu. 1-9 [doi]
- High-Rate Machine Learning for Forecasting Time-Series SignalsAtiyehsadat Panahi, Ehsan Kabir, Austin Downey, David Andrews 0001, Miaoqing Huang, Jason D. Bakos. 1-9 [doi]
- Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCsSrinirdheeshwar Kuttuva Prakash, Hiren Patel, Nachiket Kapre. 1-9 [doi]
- Highly-Multiplexed Superconducting Detector Readout: Approachable High-Speed FPGA DesignJennifer Pearl Smith, John I. Bailey III, Benjamin A. Mazin. 1-2 [doi]
- IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLSEcenur Ustun, Ismail San, Jiaqi Yin, Cunxi Yu, Zhiru Zhang. 1-10 [doi]
- TFR-GCN: A GCN Accelerator with Tile-Fusing StrategyShengjun Xu, Wenjin Huang, Yihua Huang. 1 [doi]
- A New Design Workflow for PYNQ Enabled Xilinx Platforms Utilising the Simulink Environment for Vivado IPI AbstractionLewis D. McLaughlin, Louise H. Crockett, Robert W. Stewart. 1 [doi]
- Mixed-Resource Parallel Processing on FPGAsStewart Denholm, Wayne Luk. 1 [doi]
- FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLSArchit Gajjar, Priyank Kashyap, Aydin Aysu, Paul D. Franzon, Sumon Dey, Chris Cheng. 1-9 [doi]
- Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated AttacksJens Trautmann, Jürgen Teich, Stefan Wildermann. 1-9 [doi]
- A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication EngineMaik Ender, Gregor Leander, Amir Moradi 0001, Christof Paar. 1-9 [doi]
- A Dual-Mode Similarity Search Accelerator based on Embedding Compression for Online Cross-Modal Image-Text RetrievalYeo-Reum Park, Ji-Hoon Kim, Jaeyoung Do, Joo-Young Kim. 1-9 [doi]
- Fast Arbitrary Precision Floating Point on FPGAJohannes de Fine Licht, Christopher A. Pattison, Alexandros Nikolaos Ziogas, David Simmons-Duffin, Torsten Hoefler. 1-9 [doi]
- Augmenting HLS with Zero-Overhead Application-Specific Address Mapping for Optane DCPMMNicholas Beckwith, Jialiang Zhang, Jing Jane Li. 1-9 [doi]
- Accelerating Deformable Convolution NetworksYuan Meng, Hongjiang Men, Viktor K. Prasanna. 1 [doi]
- A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory NetworksYutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Kenji Mizutani, Shigeru Nakamura, Tatsuya Usuki, Michihiro Koibuchi. 1 [doi]
- FPGA Accelerator for Homomorphic Encrypted Sparse Convolutional Neural Network InferenceYang Yang 0111, Sanmukh R. Kuppannagari, Rajgopal Kannan, Viktor K. Prasanna. 1-9 [doi]
- Resource Sharing for Verified High-Level SynthesisMichalis Pardalos, Yann Herklotz, John Wickerson. 1-6 [doi]
- Density-Aware Parallel Hyperdimensional Genome Sequence MatchingHanning Chen, Mohsen Imani. 1-4 [doi]
- Software defined optical time-domain reflectometerThomas Mauldin, Zhenyu Xu, Tao Wei. 1-5 [doi]
- Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTRSeyed Alireza Damghani, Kenneth B. Kent. 1 [doi]
- FPGA-based Accelerators System with Low Latency Autonomous DMA EngineTomoya Yokono, Yoshiro Yamabe, Kenji Tanaka, Yuki Arikawa, Teruaki Ishizaki. 1 [doi]
- Accurate Performance and Power Prediction for FPGAs Using Machine LearningLina Sawalha, Tawfiq Abuaita, Martin Cowley, Sergei Akhmatdinov, Adam Dubs. 1 [doi]
- On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAsJunning Fan, Oliver Diessel. 1 [doi]
- Scheduling of Hardware Tasks in Reconfigurable Mixed-Criticality SystemsCornelia Wulf, Najdet Charaf, Diana Goehringer. 1 [doi]
- Exploiting Scheduling Information for Efficient High-Level Synthesis Design Space ExplorationXingyue Qian, Jian Shi, Li Shi, Haoyang Zhang, Lijian Bian, Weikang Qian. 1 [doi]
- DQI: A Dynamic Quantization Method for Efficient Convolutional Neural Network Inference AcceleratorsYun Wang, Qiang Liu, Shun-Yan. 1 [doi]
- TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAsWeikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong. 1 [doi]
- A Versatile Systolic Array for Transposed and Dilated Convolution on FPGASuhail Basalama, Atefeh Sohrabizadeh, Jie Wang 0022, Jason Cong. 1-2 [doi]
- A programming model for developing Application Specific Dataflow Machines on FPGAsNick Brown. 1 [doi]
- COPA Use Case: Distributed Secure Joint ComputationRushi Patel, Pouya Haghi, Shweta Jain 0005, Andriy Kot, Venkata Krishnan, Mayank Varia, Martin C. Herbordt. 1-2 [doi]
- Hardware-Friendly Acceleration for Deep Neural Networks with Micro-Structured CompressionMengshu Sun, Sheng Lin, Shan Liu 0001, Songnan Li, Yanzhi Wang, Wei Jiang, Wei Wang 0311. 1 [doi]