Sajjad Rostami-Sani - researchr alias

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Viewing Publication 1 - 7 from 7

2024

Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nmSajjad Rostami-Sani, Andy Gean Ye. trets, 17(1), March 2024. [doi]

2022

The effect of gate voltage boosting on the power efficiency of multi-context FPGAsAnas Razzaq, Sajjad Rostami-Sani, Andy Gean Ye. integration, 86:30-43, 2022. [doi]

Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAsSajjad Rostami-Sani, Andy Gean Ye. mam, 92:104563, July 2022. [doi]

Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nmSajjad Rostami-Sani, Anas Razzaq, Andy Ye. fccm 2022: 1-9 [doi]

2021

Designing efficient FPGA tiles for power-constrained ultra-low-power applicationsAnas Razzaq, Sajjad Rostami-Sani, Andy Gean Ye. integration, 78:124-134, 2021. [doi]

2020

Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET TechnologySajjad Rostami-Sani, Farheen Fatima Khan, Anas Razzaq, Andy Ye. fpl 2020: 214-219 [doi]

2019

Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial TagsSajjad Rostami-Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti. jcsc, 28(12):1950203, 2019. [doi]

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