Abstract is missing.
- High Bandwidth Memory on FPGAs: A Data Analytics PerspectiveKaan Kara, Christoph Hagleitner, Dionysios Diamantopoulos, Dimitris Syrivelis, Gustavo Alonso. 1-8 [doi]
- NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction ModelingGagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gómez-Luna, Sander Stuijk, Onur Mutlu, Henk Corporaal. 9-17 [doi]
- Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based RoutersGurshaant Malik, Ian Elmor Lang, Rodolfo Pellizzoni, Nachiket Kapre. 18-25 [doi]
- RANTT: A RISC-V Architecture Extension for the Number Theoretic TransformEmre Karabulut, Aydin Aysu. 26-32 [doi]
- MCEA: A Resource-Aware Multicore CGRA Architecture for the EdgeGuilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 33-39 [doi]
- Endurance-Aware RRAM-Based Reconfigurable Architecture using TCAM ArraysJoão Paulo Cardoso de Lima, Marcelo Brandalero, Luigi Carro. 40-46 [doi]
- HyperLogLog Sketch Acceleration on FPGAAmit Kulkarni, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso. 47-56 [doi]
- A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGAAbbas Haghi, Lluc Alvarez, Jordà Polo, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó. 57-64 [doi]
- An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database AnalyticsPhilippos Papaphilippou, Chris Brooks, Wayne Luk. 65-72 [doi]
- A High-Performance Out-of-Order Soft Processor Without Register RenamingSatoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi 0001, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai. 73-78 [doi]
- TTA-SIMD Soft Core ProcessorsKati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen. 79-84 [doi]
- A Configurable TLB Hierarchy for the RISC-V ArchitectureNikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Dionisios N. Pnevmatikatos. 85-90 [doi]
- A Service-Oriented Memory Architecture for FPGA ComputingJoseph Melber, James C. Hoe. 91-97 [doi]
- FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT ReconstructionLinjun Qiao, Guojie Luo, Wentai Zhang 0001, Ming Jiang 0001. 98-102 [doi]
- On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAsNaoki Fujieda. 103-108 [doi]
- Accelerating Local Laplacian Filters on FPGAsShashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini. 109-114 [doi]
- A Seamless DFT/FFT Self-Adaptive Architecture for Embedded Radar ApplicationsJulien Mazuet, Michel Narozny, Catherine Dezan, Jean-Philippe Diguet. 115-120 [doi]
- Using DSP Slices as Content-Addressable Update QueuesThomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso. 121-126 [doi]
- A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAsAbhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde. 127-132 [doi]
- Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph DatasetsAtharva Gondhalekar, Wu-chun Feng. 133-137 [doi]
- A Deep-Learning Framework for Predicting Congestion During FPGA PlacementDani Maarouf, Ahmed Shamli, Timothy Martin, Gary Gréwal, Shawki Areibi. 138-144 [doi]
- RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary AlgorithmsNiansong Zhang, Xiang Chen, Nachiket Kapre. 145-152 [doi]
- Timing-Driven Placement for FPGA Architectures with Dedicated Routing PathsStefan Nikolic, Grace Zgheib, Paolo Ienne. 153-161 [doi]
- LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCsFarah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran. 162-168 [doi]
- Using Novel Configuration Techniques for Accelerated FPGA AgingTanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings. 169-175 [doi]
- Compact and Programmable yet High-Performance SoC Architecture for Cryptographic PairingsMilad Bahadori, Kimmo Järvinen 0001. 176-184 [doi]
- X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAsDina G. Mahmoud, Wei Hu, Mirjana Stojilovic. 185-192 [doi]
- Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated EncryptionFlora Coleman, Behnaz Rezvani, Sachin Sachin, William Diehl. 193-199 [doi]
- Lightweight Side-Channel Protection using Dynamic Clock RandomizationBenjamin Hettwer, Kallyan Das, Sebastien Leger, Stefan Gehrer, Tim Güneysu. 200-207 [doi]
- Automated Design of FPGAs Facilitated by Cycle-Free RoutingAng Li, Ting-Jung Chang, David Wentzlaff. 208-213 [doi]
- Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET TechnologySajjad Rostami-Sani, Farheen Fatima Khan, Anas Razzaq, Andy Ye. 214-219 [doi]
- Precise Pointer Analysis in High-Level SynthesisNadesh Ramanathan, George A. Constantinides, John Wickerson. 220-224 [doi]
- Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAsKahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton. 225-230 [doi]
- Power Wasting Circuits for Cloud FPGA AttacksGeorge Provelengios, Daniel E. Holcomb, Russell Tessier. 231-235 [doi]
- Secret Sharing MPC on FPGAs in the DatacenterPierre-Francois Wolfe, Rushi Patel, Robert Munafo, Mayank Varia, Martin C. Herbordt. 236-242 [doi]
- Mask Scrambling Against SCA on Reconfigurable TBOX-Based AESJoão Carlos Resende, Ricardo J. R. Maçãs, Ricardo Chaves. 243-248 [doi]
- FLASH: FPGA Locality-Aware Sensitive Hash for Nearest Neighbor Search and Clustering ApplicationWei Yan 0005, Fatemeh Tehranipoor, Xuan Zhang, John A. Chandy. 249-253 [doi]
- A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity PatternTao Yang, Yunkun Liao, Jianping Shi, Yun Liang 0001, Naifeng Jing, Li Jiang. 254-261 [doi]
- Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the EdgeDuvindu Piyasena, Miyuru Thathsara, Sathursan Kanagarajah, Siew Kei Lam, Meiqing Wu. 262-268 [doi]
- FP-Stereo: Hardware-Efficient Stereo Vision for Embedded ApplicationsJieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding 0001, Sharad Sinha, Wei Zhang 0012, Shaojie Shen. 269-276 [doi]
- A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable ConvolutionJustin Knapheide, Benno Stabernack, Maximilian Kuhnke. 277-283 [doi]
- Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot ManipulationYanqi Liu, Giuseppe Calderoni, Ruth Iris Bahar. 284-290 [doi]
- LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput ApplicationsYaman Umuroglu, Yash Akhauri, Nicholas James Fraser, Michaela Blott. 291-297 [doi]
- An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural NetworksRyosuke Kuramochi, Hiroki Nakahara. 298-303 [doi]
- FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency RelaxationShashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini. 304-309 [doi]
- Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler StackDionysios Diamantopoulos, Burkhard Ringlein, Mitra Purandare, Gagandeep Singh, Christoph Hagleitner. 310-316 [doi]
- Caffe Barista: Brewing Caffe with FPGAs in the Training LoopDiederik Adriaan Vink, Aditya Rajagopal, Stylianos I. Venieris, Christos-Savvas Bouganis. 317-322 [doi]
- A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOSRyusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada. 323-327 [doi]
- Partial Reconfiguration for Design OptimizationMarie Nguyen, Nathan Serafin, James C. Hoe. 328-334 [doi]
- Weighing Up the New Kid on the Block: Impressions of using Vitis for HPC Software DevelopmentNick Brown. 335-340 [doi]
- A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAsRichard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang. 341-346 [doi]
- Characterizing Latency Overheads in the Deployment of FPGA AcceleratorsRyan A. Cooke, Suhaib A. Fahmy. 347-352 [doi]
- Efficient Ab-Initio Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGAsArjun Ramaswami, Tobias Kenter, Thomas D. Kühne, Christian Plessl. 353-354 [doi]
- Design for ReConfigurability: An Electronic System Level Methodology to Exploit Reconfigurable PlatformsGabriella D'Andrea, Luigi Pomante. 355-356 [doi]
- High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical CommunicationCheolyong Bae, Oscar Gustafsson. 357-358 [doi]
- Acceleration of Simulation Models Through Automatic Conversion to FPGA HardwareFrans Skarman, Oscar Gustafsson, Daniel Jung 0002, Mattias Krysander. 359-360 [doi]
- Securing FPGA Accelerators at the Electrical Level for Multi-tenant PlatformsTuan La, Kaspar Matas, Khoa Dang Pham, Dirk Koch. 361-362 [doi]
- Resource Elastic Database AccelerationKristiyan Manev, Dirk Koch. 363-364 [doi]
- Transparent Integration of a Dynamic FPGA Database Acceleration SystemKaspar Mätas, Dirk Koch. 365-366 [doi]
- Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation FrameworkNuno Paulino 0001, João Canas Ferreira, João Bispo, João M. P. Cardoso. 367 [doi]
- A Self-Compilation Flow Demo on FOS - The FPGA Operating SystemKhoa Dang Pham, Anuj Vaishnav, Joseph Powell, Dirk Koch. 368 [doi]
- Demo: A Closer Look at Malicious BitstreamsTuan La, Kaspar Matas, Joseph Powell, Khoa Dang Pham, Dirk Koch. 369 [doi]
- RISC-V FPGA Platform Toward ROS-Based Robotics ApplicationJaewon Lee, Hanning Chen, Jeffrey S. Young 0001, Hyesoon Kim. 370 [doi]
- Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-EfficiencyErhan Baturay Onural, Ismail Emir Yuksel, Behzad Salami 0001. 371 [doi]