Table of Contents

• Non-Linear Circuit Simulation using MATLABSteven P. Levitan, Jose A. Martinez, Donald M. Chiarulli. 1-5 [doi]
• Mixed-Level Modeling Using Configurable MOS Transistor ModelsJuergen Weber, Andreas C. Lemke, Andreas Lehmler, Mario Anton, Sorin A. Huss. 6-11 [doi]
• An Extension to VHDL-AMS for AMS Systems with Partial Differential EquationsLeran Wang, Chenxu Zhao, Tom J. Kazmierski. 12-17 [doi]
• SystemC-WMS modeling of control techniques for switching amplifiers targeting polar RF transmittersTommasso Leonardi, Massimo Conti, Eva Vidal, Eduard Alarcón. 18-24 [doi]
• Proposal for a Bond Graph Based Model of Computation in SystemC-AMSTorsten Mähne, Alain Vachoux. 25-31 [doi]
• A general approach to the interoperability of HetSC and SystemC-AMSFernando Herrera, Eugenio Villar, Christoph Grimm, Markus Damm, Jan Haase. 32-37 [doi]
• Range Arithmetics to Speed up Reachability Analysis of Analog SystemsDarius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke. 38-43
• Statistical Modeling with VHDL-AMSErnst Christen, David Bedrosian, Joachim Haase. 44-49 [doi]
• APDL: A Processor Description Language For Design Space Exploration of Embedded ProcessorsNima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi. 50-55 [doi]
• Modeling Field Bus Communications for Automotive ApplicationsMohamad Alassir, Julien Denoulet, Gabriel Vasilescu, Olivier Romain, Romain Arnaud, Patrick Garda. 56-61 [doi]
• Efficient Transient Simulation of Lossy Coupled Interconnects in Digital Communication ApplicationsThomas Uhle, Karsten Einwich, Joachim Haase. 62-67 [doi]
• Common HDL-Matlab Simulation EnvironmentAdam Milik, Andrzej Pulka. 68-73 [doi]
• Modelling Alternatives for Cycle Approximate Bus TLMsMartin Radetzki, Rauf Salimi Khaligh. 74-79 [doi]
• Protocol Bus Modeling using inheritance with TLM2.0Hector Posadas, David Quijano, Eugenio Villar, Marcos Martínez. 80-85 [doi]
• Combinatorial Dependencies in Transaction Level ModelsRobert Günzel, Wolfgang Klingauf, James Aldis. 86-91 [doi]
• Transaction Level Modelling: A reflection on what TLM is and how TLMs may be classifiedMark Burton, James Aldis, Robert Günzel, Wolfgang Klingauf. 92-97 [doi]
• How Different are Esterel and SystemC?Jens Brandt, Klaus Schneider. 98-103
• Autometic Generation of SystemC Transactors from AsmL SpecificationTareq Hasan Khan, Ali Habibi, Sofiène Tahar, Otmane Aït Mohamed. 104-109 [doi]
• Timed Asynchronous Circuits Modeling using SystemCCedric Koch-Hofer, Marc Renaudin. 110-115 [doi]
• CSP with Synthesisable SystemC(tm) and OSSSClaus Brunzema, Wolfgang Nebel. 116-121 [doi]
• SystemC-based Simulation of the MICAS ArchitectureJohan Lilius, Ivan Porres, Kim Sandström, Dragos Truscan. 122-127 [doi]
• Mapping Actor-Oriented Models to TLM ArchitecturesJens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich. 128-133 [doi]
• C-based System Development of Asynchronous Distributed SystemsMario Korte, Frank Slomka. 134-139 [doi]
• An Integrated SystemC Debugging EnvironmentFrank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke. 140-145 [doi]
• Measuring the Quality of a SystemC Testbench by using Code Coverage TechniquesDaniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler. 146-151 [doi]
• Algorithmic Test Generation - a New Approach to testbench CreationStaffan Berg. 152-158 [doi]
• A Domain Specific Language for CryptographyGiovanni Agosta, Gerardo Pelosi. 159-164 [doi]
• The Unified Models Methodology: Applications to Inkjet PrintingLuis Baldez, Sascha de Pena, Joan Vidal. 165-170 [doi]
• A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design LibraryParisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi. 171-176 [doi]
• Granularity Issues in Transaction Level Modelling Digital Signal Processing ApplicationsSylvain Huet, Sebastien LeNours, Olivier Pasquier, Emmanuel Casseau. 177-184 [doi]
• UML and SystemC - Comparison and Mapping Rules for Automatic Code GenerationPer Andersson, Martin Höst. 185-190 [doi]
• A complete SystemC UML profile with dynamic features for behavioral descriptionsSara Bocchio, Elvinia Riccobene, Alberto Rosti, Patrizia Scandurra. 191-197 [doi]
• SC2 StateCharts to SystemC: Automatic Executable Models GenerationMarcello Mura, Marco Paolieri. 198-203 [doi]
• SystemC workload model generation from UML for performance simulationJari Kreku, Mika Hoppari, Kari Tiensyrjä, Per Andersson. 204-285 [doi]
• A Metamodeling based Framework for Architectural Modeling and Simulator GenerationDeepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla. 210-218 [doi]
• Compiling UML State Diagrams into VHDL: An Experiment in Using Model Driven DevelopmentDavid H. Akehurst, W. Gareth J. Howells, Klaus D. McDonald-Maier, Behzad Bordbar. 219-224 [doi]
• Mapping SysML to SystemCWaseem Raslan, Ahmed Sameh. 225-230 [doi]
• Software Real-time Resource ModelingFrédéric Thomas, Sébastien Gérard, Jérôme Delatour, François Terrier. 231-236
• Modeling Embedded Software Platforms with a UML ProfileTero Arpinen, Mikko Setälä, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen. 237-242 [doi]
• Model-driven development of embedded system on heterogeneous platformsJulio Cano, Natividad Martínez Madrid, Ralf Seepold, Fernando Lopez Aguilar. 243-248 [doi]
• Modeling of immediate vs. delayed data communications: from AADL to UML MarteFrédéric Mallet, Charles André, Robert de Simone. 249-254 [doi]
• Model Transformations from a Data Parallel Formalism towards Synchronous LanguagesHuafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser. 255-260
• Automatic High Level Assertion Generation and Synthesis for Embedded System DesignLun Li, Frank P. Coyle, Mitchell A. Thornton. 261-267 [doi]
• Time Modeling in MARTERobert de Simone, Charles André. 268-273 [doi]
• MARTE: UML-based Hardware Design from Modelling to SimulationSafouan Taha, Ansgar Radermacher, Sébastien Gérard, Jean-Luc Dekeyser. 274-279 [doi]
• Repetitive Allocation Modelling with MARTEPierre Boulet, Philippe Marquet, Éric Piel, Julien Taillard. 280-285 [doi]
• Asynchronous online-monitoring of logical and temporal assertionsKatell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione. 286-290 [doi]
• A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-SetMartin Schickel, Martin Oberkönig, Martin Schweikert, Hans Eveking. 291-292 [doi]
• Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSLGhiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, Sofiène Tahar. 293-298 [doi]
• Grid Based Fast Falsification For Bounded Property CheckingPradeep Kumar Nalla, Jörg Behrend, Prakash Mohan Peranandam, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel. 299-304 [doi]
• Transactor-based Formal Verification of Real-time Embedded SystemsDaniel Karlsson, Petru Eles, Zebo Peng. 305-310 [doi]
• Verification of the Properties of Asynchronous Real-Time Distributed Systems using the B-FormalismAyman M. Wahba, Islam A. M. El-Maddah. 311-209 [doi]