Table of Contents

• Top-down Physical Design of Soft Embedded FPGA FabricsPrashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai. 1-10 [doi]
• NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAsMorten B. Petersen, Stefan Nikolic, Mirjana Stojilovic. 11-22 [doi]
• Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAsAman Arora, Samidh Mehta, Vaughn Betz, Lizy K. John. 23-33 [doi]
• Global Is the New Local: FPGA Architecture at 5nm and BeyondStefan Nikolic, Francky Catthoor, Zsolt Tokei, Paolo Ienne. 34-44 [doi]
• FABulous: An Embedded FPGA FrameworkDirk Koch, Nguyen-Dao, Bea Healy, Jing Yu, Andrew Attwood. 45-56 [doi]
• Stratix 10 NX Architecture and ApplicationsMartin Langhammer, Eriko Nurvitadhi, Bogdan Pasca, Sergey Gribok. 57-67 [doi]
• Scientific Applications of FPGAs at the LHCPhilip Harris. 68 [doi]
• ThunderGP: HLS-based Graph Processing Framework on FPGAsXinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, Deming Chen. 69-80 [doi]
• AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAsLicheng Guo, Yuze Chi, Jie Wang 0022, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong. 81-92 [doi]
• AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGAJie Wang 0022, Licheng Guo, Jason Cong. 93-104 [doi]
• Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through MicrobenchmarkingAlec Lu, Zhenman Fang, Weihua Liu, Lesley Shannon. 105-115 [doi]
• HBM Connect: High-Performance HLS Interconnect for FPGA HBMYoung Kyu Choi, Yuze Chi, Weikang Qiao, Nikola Samardzic, Jason Cong. 116-126 [doi]
• PRGA: An Open-Source FPGA Research and Prototyping FrameworkAng Li, David Wentzlaff. 127-137 [doi]
• Interactive Debugging at IP Block Interfaces in FPGAsMarco Antonio Merlini, Isamu Poy, Paul Chow. 138-144 [doi]
• A Framework for Optimizing GCN Inference on FPGABingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna. 145 [doi]
• Probabilistic Optimization for High-Level SynthesisJianyi Cheng, John Wickerson, George A. Constantinides. 145 [doi]
• Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAsDillon Huff, Steve Dai, Pat Hanrahan. 145-146 [doi]
• APCNN: Explore Multi-Layer Cooperation for CNN Optimization and Acceleration on FPGABeilei Jiang, Xianwei Cheng, Sihai Tang, Xu Ma 0005, Zhaochen Gu, Hui Zhao 0013, Song Fu. 146-147 [doi]
• LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAsBehnam Ghavami, Seyed Milad Ebrahimi, Zhenman Fang, Lesley Shannon. 146 [doi]
• Modeling FPGA-Based Systems via Few-Shot LearningGagandeep Singh, Dionysios Diamantopoulos, Juan Gómez-Luna, Sander Stuijk, Onur Mutlu, Henk Corporaal. 146 [doi]
• AutoDSE: Enabling Software Programmers Design Efficient FPGA AcceleratorsAtefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong. 147 [doi]
• ScalaBFS: A Scalable BFS Accelerator on FPGA-HBM PlatformChenhao Liu, Zhiyuan Shao, Kexin Li, Minkang Wu, Jiajie Chen, Ruoshi Li, Xiaofei Liao, Hai Jin 0001. 147 [doi]
• Fuzzing High-Level Synthesis ToolsZewei Du, Yann Herklotz, Nadesh Ramanathan, John Wickerson. 148 [doi]
• SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGAYufei Ma, Gokul Krishnan, Yu Cao 0001, Le Ye, Ru Huang. 148 [doi]
• RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA CommunicationQianfeng Clark Shen, Jun Zheng, Paul Chow. 148 [doi]
• GraSU: A Fast Graph Update Library for FPGA-based Dynamic Graph ProcessingQinggang Wang, Long Zheng 0003, Yu Huang 0013, Pengcheng Yao, Chuangyi Gui, Xiaofei Liao, Hai Jin 0001, Wenbin Jiang, Fubing Mao. 149-159 [doi]
• Folded Integer Multiplication for FPGAsMartin Langhammer, Bogdan Pasca. 160-170 [doi]
• FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional ActivationsYichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang. 171-182 [doi]
• DYNAMAP: Dynamic Algorithm Mapping Framework for Low Latency CNN InferenceYuan Meng, Sanmukh R. Kuppannagari, Rajgopal Kannan, Viktor K. Prasanna. 183-193 [doi]
• S2N2: A FPGA Accelerator for Streaming Spiking Neural NetworksAlireza Khodamoradi, Kristof Denolf, Ryan Kastner. 194-205 [doi]
• CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAsQijing Huang 0001, Dequan Wang, Zhen Dong, Yizhao Gao, Yaohui Cai, Tian Li, Bichen Wu, Kurt Keutzer, John Wawrzynek. 206-216 [doi]
• Efficient FPGA Modular Multiplication ImplementationMartin Langhammer, Bogdan Pasca. 217-223 [doi]
• Are We Alone? Searching for ET with FPGAsDan Werthimer. 224 [doi]
• Exploring PGAS Communication for Heterogeneous Clusters with FPGAsVarun Sharma, Paul Chow. 225 [doi]
• Extending High-Level Synthesis for Task-Parallel ProgramsYuze Chi, Licheng Guo, Young Kyu Choi, Jie Wang 0022, Jason Cong. 225 [doi]
• Stealing Neural Network Structure through Remote FPGA Side-channel AnalysisYicheng Zhang, Rozhin Yasaei, Hao Chen, Zhou Li 0001, Mohammad Abdullah Al Faruque. 225 [doi]
• Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous SystemsMahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus. 226-227 [doi]
• Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-gate Memories and Voltage DivisionAyokunle Fadamiro, Pouyan Rezaie, Spencer Millican, Christopher Harris. 226 [doi]
• Resource Sharing in Dataflow CircuitsLana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne. 226 [doi]
• PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis FlowSitao Huang, Kun Wu, Hyunmin Jeong, Chengyue Wang, Deming Chen, Wen-mei Hwu. 227-228 [doi]
• NPE: An FPGA-based Overlay Processor for Natural Language ProcessingHamza Khan, Asma Khan, Zainab Khan, Lun Bin Huang, Kun Wang, Lei He. 227 [doi]
• Classifying Computations on Multi-Tenant FPGAsMustafa S. Gobulukoglu, Colin Drewes, Bill Hunter, Dustin Richmond, Ryan Kastner. 227 [doi]
• 3M-AI: A Multi-task and Multi-core Virtualization Framework for Multi-FPGA AI Systems in the CloudShulin Zeng, Guohao Dai, Hanbo Sun, Jun Liu, Hongren Zheng, Yusong Wu, Fan Zhang, Xinhao Yang, Yi Cai, Yu Wang, Huazhong Yang. 228 [doi]
• MLBlocks: FPGA Blocks for Machine Learning ApplicationsSeyedRamin Rasoulinezhad, David Boland, Philip H. W. Leong. 228 [doi]
• Reconfigurable Acceleration of Short Read Mapping with Biological ConsiderationHo-Cheung Ng, Izaak Coleman, Shuanglong Liu, Wayne Luk. 229-239 [doi]
• An FPGA-based 7-ENOB 600 MSample/s ADC without any External ComponentsLukas Leuenberger, Dorian Amiet, Tao Wei, Paul Zbinden. 240-250 [doi]
• A Framework for Customizable FPGA-based Image Registration AcceleratorsDavide Conficconi, Eleonora D'Arnese, Emanuele Del Sozzo, Donatella Sciuto, Marco D. Santambrogio. 251-261 [doi]
• NASCENT: Near-Storage Acceleration of Database Sort on SmartSSDSahand Salamat, Armin Haj Aboutalebi, Behnam Khaleghi, Joo Hwan Lee, Yang-Seok Ki, Tajana Rosing. 262-272 [doi]
• MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with AcceleratorsPeipei Zhou 0001, Jiayi Sheng, Cody Hao Yu, Peng Wei 0004, Jie Wang 0022, Di Wu 0010, Jason Cong. 273-279 [doi]
• Design Principles for Packet Deparsers on FPGAsThomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria. 280-286 [doi]