Table of Contents

• RapidStream: Parallel Physical Implementation of FPGA HLS DesignsLicheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin 0001, Jie Wang 0022, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong. 1-12 [doi]
• How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA FabricsKing Lok Chung, Nguyen-Dao, Jing Yu 0014, Dirk Koch. 13-23 [doi]
• Revisiting PathFinder Routing AlgorithmYue Zha, Jing Li. 24-34 [doi]
• Multi-input Serial Adders for FPGA-like Computational FabricHerman Schmit, Matthew Denton. 35-41 [doi]
• Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAsQingcheng Xiao, Yun Liang 0001. 42-48 [doi]
• Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi DamasceneZsolt Tokei. 49 [doi]
• A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGAMingqiang Huang, Yucen Liu, Quan Cheng, Shuxin Yang, Kai Li, Junyi Luo, Zhengke Yang, Qiufeng Li, Hao Yu, Changhai Man. 50 [doi]
• Automated Accelerator Optimization Aided by Graph Neural NetworksAtefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong. 50 [doi]
• Efficient FPGA-based ECDSA Verification Engine For Permissioned BlockchainsRashmi Agrawal, Ji Yang, Haris Javaid. 50 [doi]
• Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot ManipulationYanqi Liu, Anthony Opipari, Théo Guérin, Ruth Iris Bahar. 51 [doi]
• End-to-End Acceleration of Homomorphic Encrypted CNN Inference on FPGAsTian Ye, Rajgopal Kannan, Viktor K. Prasanna. 51 [doi]
• FPGA Accelerators for Robust Visual SLAM on Humanoid RobotsMaria Rafaela Gkeka, Alexandros Patras, Nikolaos Tavoularis, Stylianos Piperakis, Emmanouil Hourdakis, Panos E. Trahanias, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas. 51 [doi]
• MathRAMs: Configurable Fused Compute-Memory Blocks for FPGAsAman Arora, Aatman Borda, Tanmay Anand, Bagus Hanindhito, Lizy K. John. 52 [doi]
• HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance AuthenticationRakin Muhammad Shadab, Yu Zou, Sanjay Gandham, Amro Awad, Mingjie Lin. 52 [doi]
• Synthesized Garbage Collection for FPGA AcceleratorsMartha Barker, Stephen A. Edwards, Martha A. Kim. 53 [doi]
• High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMVYixiao Du, Yuwei Hu, Zhongchun Zhou, Zhiru Zhang. 54-64 [doi]
• Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix MultiplicationLinghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young Kyu Choi, Jason Lau, Jason Cong. 65-77 [doi]
• HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAsShaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang. 78-88 [doi]
• Finding and Finessing Static Islands in Dynamically Scheduled CircuitsJianyi Cheng, John Wickerson, George A. Constantinides. 89-100 [doi]
• Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network InferenceErwei Wang, James J. Davis 0001, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed Abdelfattah. 101-111 [doi]
• N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing CoresYu Gong, Zhihan Xu, Zhezhi He, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, Li Jiang. 112-122 [doi]
• HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous PlatformYi-Chien Lin, Bingyi Zhang, Viktor K. Prasanna. 123-133 [doi]
• FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision QuantizationMengshu Sun, Zhengang Li, Alec Lu, Yanyu Li, Sung-En Chang, Xiaolong Ma, Xue Lin, Zhenman Fang. 134-145 [doi]
• An FPGA-based RNN-T Inference Accelerator with PIM-HBMShinhaeng Kang, Sukhan Lee 0002, Byeongho Kim, Hweesoo Kim, Kyomin Sohn, Nam Sung Kim, Eojin Lee. 146-152 [doi]
• The Virtuous Cycles of Determinism: Programming Groq's Tensor Streaming ProcessorSatnam Singh. 153 [doi]
• DecGNN: A Framework for Mapping Decoupled GNN Models onto CPU-FPGA Heterogeneous PlatformBingyi Zhang, Hanqing Zeng, Viktor K. Prasanna. 154 [doi]
• Highly Scalable Runtime Countermeasure Against Microprobing Attacks on Die-to-Die Interconnections in System-in-PackageZhenyu Xu, Thomas Mauldin, Qing Yang 0001, Tao Wei. 154 [doi]
• FPGA-based Trainable Autoencoder for Communication SystemsJonas Ney, Sebastian Dörner, Matthias Herrmann, Mohammad Hassani Sadi, Jannis Clausius, Stephan ten Brink, Norbert Wehn. 154 [doi]
• MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGAMohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami. 155 [doi]
• An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGAYukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu. 155 [doi]
• HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS DevelopersYuanlong Xiao, André DeHon. 155 [doi]
• Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA PlatformJiafeng Xie, Pengzhou He, Tianyou Bao. 156 [doi]
• SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity ComputationAtefeh Sohrabizadeh, Yuze Chi, Jason Cong. 156 [doi]
• Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTRSeyed Alireza Damghani, Kenneth B. Kent. 157 [doi]
• REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAsYizhao Gao, Song Wang, Hayden Kwok-Hay So. 158-168 [doi]
• Accelerating Constraint-Based Causal Discovery by Shifting Speed BottleneckCe Guo, Wayne Luk. 169-179 [doi]
• Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGAMarius Knaust, Enrico Seiler, Knut Reinert, Thomas Steinke 0001. 180-189 [doi]
• Accelerating SSSP for Power-Law GraphsYuze Chi, Licheng Guo, Jason Cong. 190-200 [doi]