Abstract is missing.
- Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the EdgeJeffrey Chen, Sehwan Hong, Warrick He, Jinyeong Moon, Sang-Woo Jun. 1-8 [doi]
- FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory AccessJian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo. 9-16 [doi]
- An FPGA-based MobileNet Accelerator Considering Network Structure CharacteristicsShun-Yan, Zhengyan Liu, Yun Wang, Chenglong Zeng, Qiang Liu, Bowen Cheng, Ray C. C. Cheung. 17-23 [doi]
- A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning ApplicationsAtiyehsadat Panahi, Suhail Balsalama, Ange-Thierry Ishimwe, Joel Mandebi Mbongue, David Andrews 0001. 24-27 [doi]
- DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate ArraysMyat Thu Linn Aung, Chuping Qu, Liwei Yang, Tao Luo, Rick Siow Mong Goh, Weng-Fai Wong. 28-32 [doi]
- MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural NetworksChen Wu, Jinming Zhuang, Kun Wang 0005, Lei He 0001. 33-37 [doi]
- Choice - A Tunable PUF-Design for FPGAsFranz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich. 38-44 [doi]
- Power-Aware Computing Systems on FPGAs: A SurveyGökhan Akgün, Muhammad Ali 0010, Diana Göhringer. 45-51 [doi]
- HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece CryptosystemVatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández. 52-59 [doi]
- Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation SchemeZhengtai Chang, Shanshan Shi, Binwei Song, Wenbing Fan, Yao Wang. 60-63 [doi]
- EnergyNN: Energy Estimation for Neural Network Inference Tasks on DPUShikha Goel, M. Balakrishnan, Rijurekha Sen. 64-68 [doi]
- FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoTDuc-Minh Ngo, Andriy Temko, Colin C. Murphy, Emanuel M. Popovici. 69-75 [doi]
- End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum SuppressionAnupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo. 76-82 [doi]
- Performance assessment of FPGAs as HPC accelerators using the FPGA Empirical RooflineEnrico Calore, Sebastiano Fabio Schifano. 83-90 [doi]
- A High-performance Open-channel Open-way NAND Flash Controller ArchitectureYunhui Qiu, Wenbo Yin, Lingli Wang. 91-98 [doi]
- Communication-avoiding micro-architecture to compute Xcorr scores for peptide identificationSumesh Kumar, Fahad Saeed. 99-103 [doi]
- An Emulation of Quantum Error-Correction on an FPGA deviceMichael Hart, John Mc Allister, Leo Rogers, Charles Gillan. 104-108 [doi]
- OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography accelerationDaouda Diakite, Nicolas Gac, Maxime Martelli. 109-114 [doi]
- Performance Modeling and FPGA Acceleration of Homomorphic Encrypted ConvolutionTian Ye, Sanmukh R. Kuppannagari, Rajgopal Kannan, Viktor K. Prasanna. 115-121 [doi]
- Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its ApplicationsSanjay Deshpande, Santos Merino Del Pozo, Víctor Mateu, Marc Manzano, Najwa Aaraj, Jakub Szefer. 122-129 [doi]
- Dense FPGA Compute Using Signed Byte TuplesMartin Langhammer, Simon Finn, Sergey Gribok, Bogdan Pasca. 130-138 [doi]
- Demonstrating custom SIMD instruction development for a RISC-V softcorePhilippos Papaphilippou, Paul H. J. Kelly, Wayne Luk. 139 [doi]
- DO-GPU: Domain Optimizable Soft GPUsRui Ma, Jia-Ching Hsu, Tian Tan 0007, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou. 140-144 [doi]
- RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture EducationSarah L. Harris, Daniel Chaver, Luis Piñuel, J. I. Gomez-Perez, M. Hamza Liaqat, Zubair L. Kakakhel, Olof Kindgren, Robert Owen. 145-150 [doi]
- An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise AlignmentAbbas Haghi, Santiago Marco-Sola, Lluc Alvarez, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó. 151-159 [doi]
- Minimal Overhead Optical Time-Domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmable Voltage OffsetThomas Mauldin, Zhenyu Xu, Tao Wei. 160-166 [doi]
- An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image DenoisingNobuho Hashimoto, Shinya Takamaeda-Yamazaki. 167-173 [doi]
- OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-VectorsDavid Castells-Rufas, Santiago Marco-Sola, Quim Aguado-Puig, Antonio Espinosa-Morales, Juan Carlos Moure, Lluc Alvarez, Miquel Moretó. 174-178 [doi]
- An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable DependenciesAnh Hoang Ngoc Nguyen, Yuko Hara-Azumi. 179-184 [doi]
- Carnac: Algorithm Variability for Fast Swarm Verification on FPGAEmilien Fournier, Ciprian Teodorov, Loïc Lagadec. 185-189 [doi]
- An FPGA-based Hybrid Memory Emulation SystemFei Wen, Mian Qin, Paul Gratz, A. L. Narasimha Reddy. 190-196 [doi]
- EasyNet: 100 Gbps Network for HLSZhenhao He, Dario Korolija, Gustavo Alonso. 197-203 [doi]
- A Specialized Memory Hierarchy for Stream AggregationPrajith Ramakrishnan Geethakumari, Ioannis Sourdis. 204-210 [doi]
- Graph Sampling with Fast Random Walker on HBM-enabled FPGA AcceleratorsChunyou Su, Hao Liang, Wei Zhang, Kun Zhao, Baole Ai, Wenting Shen, Zeke Wang. 211-218 [doi]
- Speed Records in Network Flow Measurement on FPGAArish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, Nele Mentens. 219-224 [doi]
- Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch PresenceStefan Nikolic, Paolo Ienne. 225-233 [doi]
- Two-level MUX Design and Exploration in FPGA Routing ArchitectureYuhang Shen, Jiadong Qian, Kaichuang Shi, Lingli Wang, Hao Zhou. 234-241 [doi]
- Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAsMinghua Shen, Nong Xiao. 242-248 [doi]
- A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable SystemsCornelia Wulf, Michael Willig, Diana Göhringer. 249-256 [doi]
- Pharos: a Multi-FPGA Performance MonitorArzhang Rafii, Welson Sun, Paul Chow. 257-262 [doi]
- Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware AcceleratorsVasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris. 263-264 [doi]
- Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core ArchitecturesAhmed Kamaleldin, Diana Göhringer. 265-266 [doi]
- A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable ArraysFlorian Fricke. 267-268 [doi]
- Reconfigurable Computing Systems as Component-oriented Designs for RoboticsAriel Podlubne, Diana Göhringer. 269-270 [doi]
- Optimizing Deep Learning Decoders for FPGA ImplementationE. Kavvousanos, Vassilis Paliouras. 271-272 [doi]
- Wormhole Computing in Networks-on-ChipJens Rettkowski, Diana Göhringer. 273-274 [doi]
- Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware ArchitecturesKeyvan Shahin, Michael Hübner 0001. 275-276 [doi]
- Towards the Efficient Multi-Platform Execution of Deep Neural NetworksHector Gerardo Muñoz Hernandez. 277-278 [doi]
- Distributed Recommendation Inference on FPGA ClustersYu Zhu, Zhenhao He, Wenqi Jiang, Kai Zeng, Jingren Zhou, Gustavo Alonso. 279-285 [doi]
- SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAsSathish Panchapakesan, Zhenman Fang, Jian Li. 286-293 [doi]
- Accelerating Continual Learning on Edge FPGADuvindu Piyasena, Siew Kei Lam, Meiqing Wu. 294-300 [doi]
- Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array ArchitecturesLinqiao Liu, Stephen Brown. 301-305 [doi]
- Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial ReconfigurationHasan Irmak, Daniel Ziener, Nikolaos Alachiotis. 306-311 [doi]
- Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOsAmeer M. S. Abdelhadi, He Li. 312-318 [doi]
- A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA PlatformsAlexander Klemd, Bernd Klauer, Johannes Timmermann, Delf Sachau. 319-326 [doi]
- Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear ProgrammingGrace Zgheib, Yu Shen Lu, Ilya Ganusov. 327-333 [doi]
- Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit RepresentationJin-Hee Kim, Jason Helge Anderson. 334-340 [doi]
- Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLSJianyi Cheng, John Wickerson, George A. Constantinides. 341-346 [doi]
- MAFIA: Machine Learning Acceleration on FPGAs for IoT ApplicationsNikhil Pratap Ghanathe, Vivek Seshadri, Rahul Sharma 0001, Steve Wilton, Aayan Kumar. 347-354 [doi]
- Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD ResearchAman Arora, Andrew Boutros, Daniel Rauch, Aishwarya Rajen, Aatman Borda, Seyed Alireza Damghani, Samidh Mehta, Sangram Kate, Pragnesh Patel, Kenneth B. Kent, Vaughn Betz, Lizy K. John. 355-362 [doi]
- HALF: Holistic Auto Machine Learning for FPGAsJonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger 0004, Norbert Wehn. 363-368 [doi]
- MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration FrameworkBehnam Ghavami, Milad Ibrahimipour, Zhenman Fang, Lesley Shannon. 369-373 [doi]
- AITIA: Embedded AI Techniques for Industrial ApplicationsMarcelo Brandalero, Mitko Veleski, Hector Gerardo Muñoz Hernandez, Muhammad Ali 0010, Laurens Le Jeune, Toon Goedemé, Nele Mentens, Jurgen Vandendriessche, Lancelot Lhoest, Bruno da Silva, Abdellah Touhafi, Diana Goehringer, Michael Hübner 0001. 374-375 [doi]
- FPGA acceleration in EVOLVE's Converged Cloud-HPC InfrastructureKonstantina Koliogeorgi, Fekhr Eddine Keddous, Dimosthenis Masouros, Antony Chazapis, Michelle Aubrun, Sotirios Xydis, Angelos Bilas, Romain Hugues, Jean-Thomas Acquaviva, Huy Nam Nguyen, Dimitrios Soudris. 376-377 [doi]
- Architectures for SLAM and Augmented Reality ComputingNikolaos Bellas, Christos D. Antonopoulos, Spyros Lalis, Maria Rafaela Gkeka, Alexandros Patras, Georgios Keramidas, Iakovos Stamoulis, Nikolaos Tavoularis, Stylianos Piperakis, Emmanouil Hourdakis, Panos E. Trahanias, Paul Zikas, George Papagiannakis, Ioanna Kartsonaki. 378-379 [doi]
- HiPReP: High-Performance Reconfigurable Processor - Architecture and CompilerPhilipp S. Käsgen, Mohamed Messelka, Markus Weinhardt. 380-381 [doi]
- XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software SystemsJürgen Becker 0001, Leonard Masing, Tobias Dörr, Florian Schade, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikolaos S. Voros, Umut Durak, Alexander Ahlbrecht, Wanja Zaeske, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Florian Oszwald, Dominik Reinhardt, Mohamad Chamas, Adnan Bekan, Graham Smethurst, Fahad Siddiqui, Rafiullah Khan, Vahid Garousi, Sakir Sezer, Victor Morales. 382-383 [doi]
- The SMART4ALL High Performance Computing Infrastructure: Sharing high-end hardware resources via cloud-based microservicesAngelos S. Voros, Christos Panagiotou, Stavros Zogas, Georgios Keramidas, Christos P. Antonopoulos, Michael Hübner 0001, Nikolaos S. Voros. 384-385 [doi]
- Demonstration of a Distributed Accelerator Framework for Energy-efficient ML ProcessingFritjof Steinert, Justin Knapheide, Benno Stabernack. 386 [doi]
- Capture and Visualisation of Radio Signals with an Open Source, Single Chip Spectrum AnalyserDavid Northcote, Lewis McLaughlin, Louise H. Crockett, Robert W. Stewart. 387 [doi]
- Hand Sign Recognition via Deep Learning on Tightly Coupled Processor ArraysChristian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich. 388 [doi]
- Reduced-voltage OmpSs@FPGA: A DemonstrationMarc Perelló Bacardit, Behzad Salami 0001. 389 [doi]
- HLS_PRINT: High Performance Logging Framework on FPGANupur Sumeet, Manoj Nambiar. 390 [doi]
- Simodense: a RISC-V softcore optimised for exploring custom SIMD instructionsPhilippos Papaphilippou, Paul H. J. Kelly, Wayne Luk. 391-397 [doi]
- Hardware-software implementation of a DNN for 3D object detection using FINN - a demoJoanna Stanisz, Konrad Lis, Tomasz Kryjak, Marek Gorgon. 398 [doi]
- MELODI: An Online Platform for Mass Education of Digital Design - HDL to Remote FPGAFriedrich Bauer, Felix Braun, Daniel Hauer, Axel Jantsch, Markus D. Kobelrausch, Martin Mosbeck, Nima Taherinejad, Philipp-Sebastian Vogt. 399 [doi]
- Taping out an FPGA in 24 hours with OpenFPGA: The SOFA ProjectXifan Tang, Ganesh Gore, Grant Brown, Pierre-Emmanuel Gaillardon. 400 [doi]
- A comparison of real-time 4K/UltraHD connected component labelling architecturesMarcin Kowalczyk, Tomasz Kryjak. 401 [doi]
- Power-Aware Real-Time Operating Systems on Reconfigurable ArchitecturesGökhan Akgün, Diana Göhringer. 402-403 [doi]
- FGYM: Toolkit for Benchmarking FPGA based Reinforcement Learning AlgorithmsNathaniel Peura, Yuan Meng, Sanmukh R. Kuppannagari, Viktor K. Prasanna. 404 [doi]
- Quantised Siamese Tracker for 4K/UltraHD Video Stream - a demoDominika Przewlocka-Rus, Tomasz Kryjak. 405 [doi]
- The FABulous Open eFPGA Ecosystem in Action - From Specifications to Chips to Running BitsteamsJing Yu, Andrew Attwood, Nguyen-Dao, Dirk Koch. 406 [doi]