Table of Contents

• XVDPU: A High Performance CNN Accelerator on the Versal Platform Powered by the AI EngineXijie Jia, Yu Zhang, Guangdong Liu, Xinlin Yang, Tianyu Zhang, Jia Zheng, Dongdong Xu, Hong Wang, Rongzhang Zheng, Satyaprakash Pareek, Lu Tian, Dongliang Xie, Hong Luo, Yi Shan. 1-9 [doi]
• Ultra Low Latency Machine Learning for Scientific Edge ApplicationsNarasinga Rao Miniskar, Aaron R. Young, Frank Liu, Willem Blokland, Anthony M. Cabrera, Jeffrey S. Vetter. 1-7 [doi]
• Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGABingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart. 1-8 [doi]
• A Framework for Neural Network Inference on FPGA-Centric SmartNICsAnqi Guo, Tong Geng, Yongan Zhang, Pouya Haghi, Chunshu Wu, Cheng Tan 0002, Yingyan Lin, Ang Li, Martin C. Herbordt. 1-8 [doi]
• Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formatsSahand Kashani, Mahyar Emami, James R. Larus. 1-8 [doi]
• BunchBloomer: Cost-Effective Bloom Filter Accelerator for Genomics ApplicationsSeongyoung Kang, Tarun Sai Ganesh Nerella, Shashank Uppoor, Sang-Woo Jun. 9-16 [doi]
• TRAC: Compilation-Based Design of Transformer Accelerators for FPGAsPatrick Plagwitz, Frank Hannig, Jürgen Teich. 17-23 [doi]
• GraphScale: Scalable Bandwidth-Efficient Graph Processing on FPGAsJonas Dann, Daniel Ritter 0001, Holger Fröning. 24-32 [doi]
• Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGAYehua Ling, Yuanxing Yan, Kai Huang, Gang Chen. 33-39 [doi]
• Resource Optimal Squarers for FPGAsAndreas Böttcher, Martin Kumm, Florent de Dinechin. 40-46 [doi]
• Synthesized In-BramGarbage Collection for Accelerators with Immutable MemoryMartha Barker, Stephen A. Edwards, Martha A. Kim. 47-53 [doi]
• Virtualization of Reconfigurable Mixed-Criticality SystemsCornelia Wulf, Najdet Charaf, Diana Göhringer. 54-60 [doi]
• TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling FrameworkYunhui Qiu, Yuhang Cao, Yuan Dai, Wenbo Yin, Lingli Wang. 61-69 [doi]
• HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA CompilationYuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon. 70-78 [doi]
• TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation OptimizationsChan-Wei Hu, Jiang Hu, Sunil P. Khatri. 79-85 [doi]
• A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable ParametersZhaoteng Meng, Lin Shu, Jie Hao. 86-93 [doi]
• Real-Time Waveform Matching with a Digitizer at 10 GS/sJens Trautmann 0001, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann. 94-100 [doi]
• Optimized Mappings for Symmetric Range-Limited Molecular Force Calculations on FPGAsChunshu Wu, Sahan Bandara, Tong Geng, Anqi Guo, Pouya Haghi, Vipin Sachdeva, Woody Sherman, Martin C. Herbordt. 101-108 [doi]
• Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme QuantizationZhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang 0005, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang. 109-116 [doi]
• Reduction of Bitstream Size for Low-Cost iCE40 FPGAsClemens Fritzsch, Jörn Hoffmann 0001, Martin Bogdan. 117-122 [doi]
• A-U3D: A Unified 2D/3D CNN Accelerator on the Versal Platform for Disparity EstimationTianyu Zhang, Dong Li, Hong Wang, Yunzhi Li, Xiang Ma, Wei Luo, Yu Wang, Yang Huang, Yi Li, Yu Zhang, Xinlin Yang, Xijie Jia, Qiang Lin, Lu Tian, Fan Jiang, Dongliang Xie, Hong Luo, Yi Shan. 123-129 [doi]
• FPGA Roofline modeling and its Application to Visual SLAMIoanna-Maria Panagou, Maria Rafaela Gkeka, Alexandros Patras, Spyros Lalis, Christos D. Antonopoulos, Nikolaos Bellas. 130-135 [doi]
• The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic GatesFan Liu, Sunrui Zhang, Xiaole Cui. 136-142 [doi]
• Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM SwitchesKohei Ito, Ryota Yasudo, Hideharu Amano. 143-147 [doi]
• Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory PatternsRobert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede. 148-152 [doi]
• Model-based Generation of Hardware/Software Architectures for Robotics SystemsAriel Podlubne, Johannes Mey, Sergio Pertuz, Uwe Aßmann, Diana Göhringer. 153-159 [doi]
• DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP BlocksJan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich. 160-166 [doi]
• Auto-Tuning of Raw Filters for FPGAsTobias Hahn, Stefan Wildermann, Jürgen Teich. 167-175 [doi]
• Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous PlatformYuan Meng, Rajgopal Kannan, Viktor K. Prasanna. 176-182 [doi]
• DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O AcceleratorsBabar Khan, Carsten Heinz, Andreas Koch 0001. 183-191 [doi]
• H-GCN: A Graph Convolutional Network Accelerator on Versal ACAP ArchitectureChengming Zhang 0006, Tong Geng, Anqi Guo, Jiannan Tian, Martin C. Herbordt, Ang Lit, Dingwen Tao. 200-208 [doi]
• FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration InfrastructureYashael Faith Arthanto, David Ojika, Joo-Young Kim 0001. 218-224 [doi]
• Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory SystemsTorben Kalkhof, Andreas Koch 0001. 225-234 [doi]
• POLSCA: Polyhedral High-Level Synthesis with Compiler TransformationsRuizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides. 235-242 [doi]
• Dynamic Inter-Block Scheduling for HLSJianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson. 243-252 [doi]
• Unleashing Parallelism in Elastic Circuits with Faster Token DeliveryAyatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne. 253-261 [doi]
• Optimal Binding and Port Assignment for Loop Pipelining in High-Level SynthesisNicolai Fiege, Patrick Sittel, Peter Zipf. 262-269 [doi]
• A Unified Approach for Managing Heterogeneous Processing Elements on FPGAsStewart Denholm, Wayne Luk. 270-276 [doi]
• Maia: Matrix Inversion Acceleration Near MemoryBahar Asgari, Dheeraj Ramchandani, Amaan Marfatia, Hyesoon Kim. 277-281 [doi]
• GRAEBO: FPGA General Routing Architecture Exploration via Bayesian OptimizationSu Zheng, Jiadong Qian, Hao Zhou, Lingli Wang. 282-286 [doi]
• Dynamic Heap Management in High-Level Synthesis for Many-Accelerator ArchitecturesArgyris Kokkinis, Dionysios Diamantopoulos, Kostas Siozios. 287-293 [doi]
• A High-Performance FPGA Accelerator for CUR DecompositionM. A. A Abdelgawad, Ray C. C. Cheung, Hong Yan 0001. 294-299 [doi]
• A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore SystemsAhmed Kamaleldin, Diana Göhringer. 300-306 [doi]
• SDMA: An Efficient and Flexible Sparse-Dense Matrix-Multiplication Architecture for GNNsYingxue Gao, Lei Gong, Chao Wang, Teng Wang, Xuehai Zhou. 307-312 [doi]
• FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAsPeng Zhang, Shijun Zhang, Shang Li, Jin Zhang, Shaoxun Liu, Youjun Bu. 313-321 [doi]
• Speeding Up Optimal Modulo Scheduling with Rational Initiation IntervalsNicolai Fiege, Patrick Sittel, Peter Zipf. 322-326 [doi]
• Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAsZhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander D. Tapper, Wayne Luk. 327-333 [doi]
• EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAsYee Yang Tan, Felix Staudigl, Lukas Jünger 0001, Anna Drewes, Rainer Leupers, Jan Moritz Joseph. 334-341 [doi]
• ERMES: Efficient Racetrack Memory Emulation System based on FPGAFanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar 0001. 342-349 [doi]
• Increasing Flexibility of Cloud FPGA VirtualizationJinjie Ruan, Yisong Chang, Ke Zhang, Kan Shi, Mingyu Chen 0001, Yungang Bao. 350-357 [doi]
• Design of High-Throughput Mixed-Precision CNN Accelerators on FPGACecilia Latotzke, Tim Ciesielski, Tobias Gemmeke. 358-365 [doi]
• Feature dimensionality in CNN acceleration for high-throughput network intrusion detectionLaurens Le Jeune, Toon Goedemé, Nele Mentens. 366-374 [doi]
• A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow CircuitsCarmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic. 375-383 [doi]
• Tunable Fine-grained Clock Phase-shifting for FPGAsBardia Babaei, Dirk Koch. 384-390 [doi]
• Assessing the Effectiveness of Active Fences Against SCAs for Multi-Tenant FPGAsChristos Diktopoulos, Konstantinos Georgopoulos, Andreas Brokalakis, Georgios Christou, Grigorios Chrysos 0001, Ioannis Morianos, Sotiris Ioannidis. 391-396 [doi]
• Breaking an FPGA-Integrated NIST SP 800-193 Compliant TRNG Hard-IP Core with On-Chip Voltage-Based Fault AttacksDennis R. E. Gnad, Jiaqi Hu, Mehdi B. Tahoori. 397-403 [doi]
• Modeling and Exploration of Elastic CGRAsOmar Ragheb, Tianyi Yu, David Ma, Jason Helge Anderson. 404-410 [doi]
• SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming ArchitecturesAlexander Montgomerie-Corcoran, Zhewen Yu, Christos-Savvas Bouganis. 418-424 [doi]
• A Lightweight Multi-Attack CAN Intrusion Detection System on Hybrid FPGAsShashwat Khandelwal, Shanker Shreejith. 425-429 [doi]
• RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration DevicesAndrew Boutros, Eriko Nurvitadhi, Vaughn Betz. 438-444 [doi]
• SkeletonGCN: A Simple Yet Effective Accelerator For GCN TrainingChen Wu, Zhuofu Tao, Kun Wang 0005, Lei He 0001. 445-451 [doi]
• Mining CryptoNight-Haven on the Varium C1100 Blockchain Accelerator CardLucas Bex, Furkan Turan, Michiel Van Beirendonck, Ingrid Verbauwhede. 452-453 [doi]
• Spade: An HDL Inspired by Modern Software LanguagesFrans Skarman, Oscar Gustafsson. 454-455 [doi]
• High Performance FPGA-based Post Quantum Cryptography ImplementationsZiying Ni, Ayesha Khalid, Máire O'Neill. 456-457 [doi]
• A Framework for Intrinsic Evolvable SystemsNajdet Charaf, Diana Göhringer. 458-459 [doi]
• Virtualization of Embedded Reconfigurable SystemsCornelia Wulf, Diana Göhringer. 460-461 [doi]
• Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable HardwareDonal Campbell, Ciara Rafferty, Ayesha Khalid, Máire O'Neill. 462-463 [doi]
• Precise Characterizing of FPGAs in Production SystemsBardia Babaei, Dirk Koch. 464-465 [doi]
• FPL Demo: Runtime Stream Processing with Resource-Elastic Pipelines on FPGAsKaspar Mätas, Kristiyan Manev, Joseph Powell, Dirk Koch. 466 [doi]
• FPL Demo: An FPGA-IP Prototype Chip for MEC devicesMorihiro Kuga, Masahiro Iida, Hideharu Amano. 467 [doi]
• FPL Demo: Hot Reconfiguration - Partial Reconfiguration without BoundsMyrtle Shah. 468 [doi]
• FPL Demo: FPGA Bitstream Virus ScanningJoseph Powell, Kaspar Matas, Kristiyan Manev, Dirk Koch. 469 [doi]
• FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist GenerationMarie Auffret, Erwei Wang, James J. Davis 0001. 470 [doi]
• FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAsZelin Wang, Ke Zhang, Yisong Chang, Yanlong Yin, Yuxiao Chen, Ran Zhao, Songyue Wang, Mingyu Chen, Yungang Bao. 471 [doi]
• FPL Demo: Kyokko - An Aurora 64b66b compatible 100 Gbps Communication ControllerAkinobu Tomori, Yasunori Osana. 472 [doi]
• FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAsTakefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro. 473 [doi]
• FPL Demo: 400G FPGA Packet Capture Based on Network Development KitJakub Cabal, Jiri Sikora, Stepán Friedl, Martin Spinler, Jan Korenek. 474 [doi]