Table of Contents

• Exploring the Versal AI Engines for Signal Processing in Radio AstronomyVictor Van Wijhe, Vincent Sprave, Daniele Passaretti, Nikolaos Alachiotis, Gerrit Grutzeck, Thilo Pionteck, Steven van der Vlugt. 1-10 [doi]
• JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAsTobias Hahn, Stefan Wildermann, Jürgen Teich. 11-18 [doi]
• KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGAFanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri. 19-23 [doi]
• DynaRapid: Fast-Tracking from C to Routed CircuitsAndrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne. 24-32 [doi]
• The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAsSoheil Gholami Shahrouz, Vaughn Betz. 33-42 [doi]
• Better Together: Combining Analytical and Annealing Methods for FPGA PlacementRachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan. 43-52 [doi]
• A High-Performance Routing Engine for Large-Scale FPGAsTimothy Martin, Dani Maarouf, Gary Gréwal, Shawki Areibi. 53-59 [doi]
• SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAsPhilip Stachura, Guanyu Li, Xin Wu, Christian Plessl, Zhenman Fang. 60-68 [doi]
• H2PIPE: High Throughput CNN Inference on FPGAs with High-Bandwidth MemoryMario Doumet, Marius Stan, Mathew Hall, Vaughn Betz. 69-77 [doi]
• FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAsCanberk Sönmez, Mohamed Shahawy, Cemalettin Cem Belentepe, Paolo Ienne. 78-86 [doi]
• SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAsQianyu Cheng, Zhendong Zheng, Tianhao Jiang, Cheng Tang, Teng Wang, Lei Gong, Chao Wang, Xuehai Zhou. 87-91 [doi]
• Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAsOwen P. Lucas, Alan D. George. 92-99 [doi]
• StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAsJan-Oliver Opdenhövel, Christoph Alt, Christian Plessl, Tobias Kenter. 100-108 [doi]
• Efficient Design Space Exploration for Dynamic & Speculative High-Level SynthesisDylan Leothaud, Jean-Michel Gorius, Simon Rokicki, Steven Derrien. 109-117 [doi]
• Fast Switching Activity Estimation for HLS-Produced Dataflow CircuitsJiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, Lana Josipovic. 118-125 [doi]
• FlexWalker: An Efficient Multi-Objective Design Space Exploration Framework for HLS DesignZheyuan Zou, Cheng Tang, Lei Gong, Chao Wang, Xuehai Zhou. 126-132 [doi]
• Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verificationChao Fu, Zengshi Wang, Jun Han 0003. 133-139 [doi]
• NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable FunctionsMarta Andronic, George A. Constantinides. 140-148 [doi]
• PolyLUT-Add: FPGA-based LUT Inference with Wide InputsBinglei Lou, Richard Rademacher, David Boland, Philip H. W. Leong. 149-155 [doi]
• Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed PrecisionXilai Dai, Yuzong Chen 0001, Mohamed S. Abdelfattah. 156-163 [doi]
• UniGuard: A Unified Hardware-oriented Threat Detector for FPGA-based AI AcceleratorsXiaobei Yan, Han Qiu 0001, Tianwei Zhang 0004. 164-170 [doi]
• A Better Kyber Butterfly for FPGAsJonas Bertels, Quinten Norga, Ingrid Verbauwhede. 171-177 [doi]
• Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGAHayden Cook, Jeffrey Goeders. 178-186 [doi]
• A Software-Programmable Neural Processing Unit for Graph Neural Network Inference on FPGAsTaikun Zhang, Andrew Boutros, Sergey Gribok, Kwadwo Boateng, Vaughn Betz. 187-196 [doi]
• Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix EnginesJindong Li, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang 0080, Yi Zeng 0001. 197-203 [doi]
• SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit ConvolutionsGeng Yang, Jie Lei 0001, Zhenman Fang, Jiaqing Zhang, Junrong Zhang, Weiying Xie, Yunsong Li. 204-212 [doi]
• CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator DesignYiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang. 213-219 [doi]
• IMAGine: An In-Memory Accelerated GEMV Engine OverlayM. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001. 220-226 [doi]
• AMA: An Analytical Approach to Maximizing the Efficiency of Deep Learning on Versal AI EngineXiaodong Deng, Shijie Wang, Tianyi Gao, Jing Liu, Longjun Liu, Nanning Zheng 0001. 227-235 [doi]
• A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement LearningSamuel Wiggins, Yuan Meng 0001, Mahesh A. Iyer, Viktor K. Prasanna. 236-242 [doi]
• Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGAKejia Shi, Manting Zhang, Keqing Zhao, Xiaoxing Wu, Yang Liu, Jun Yu, Kun Wang. 243-249 [doi]
• An Open-Source And Extensible Framework for Fast Prototyping and Benchmarking of Spiking Neural Network HardwareShadi Matinizadeh, Anup Das 0001. 250-256 [doi]
• HASS: Hardware-Aware Sparsity Search for Dataflow DNN AcceleratorZhewen Yu, Sudarshan Sreeram, Krish Agrawal, Junyi Wu, Alexander Montgomerie-Corcoran, Cheng Zhang, Jianyi Cheng, Christos-Savvas Bouganis, Yiren Zhao. 257-263 [doi]
• SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAsGeng Yang, Yanyue Xie, Zhong Jia Xue, Sung-En Chang, Yanyu Li, Peiyan Dong, Jie Lei, Weiying Xie, Yanzhi Wang, Xue Lin, Zhenman Fang. 264-273 [doi]
• 3HDC: Energy Efficient Encoding for Hyper-Dimensional Computing on Edge DevicesMahboobe Sadeghipour Roodsari, Jonas Krautter, Vincent Meyers, Mehdi B. Tahoori. 274-280 [doi]
• Energy-Aware Synchronization of Hardware Tasks in Virtualized Embedded SystemsCornelia Wulf, Gökhan Akgün, Mehdi Safarpour, Anastacia Grishchenko, Diana Göhringer. 281-287 [doi]
• FPGA Modular Multipliers using Hybrid Reduction TechniquesSergey Gribok, Martin Langhammer, Bogdan Pasca 0001. 288-296 [doi]
• Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAsShivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra. 297-303 [doi]
• Exploring FPGA designs for MX and beyondEbby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides. 304-310 [doi]
• Fast and Practical Strassen's Matrix Multiplication using FPGAsAfzal Ahmad, Linfeng Du, Wei Zhang. 311-317 [doi]
• FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data EnginesAbdul Wadood, Alec Lu, Ken Zhang, Zhenman Fang. 318-324 [doi]
• BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic SchedulingKenneth Liu, Alec Lu, Zhenman Fang. 325-331 [doi]
• LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication OptimizationZhendong Zheng, Qianyu Cheng, Teng Wang, Lei Gong, Xianglan Chen, Cheng Tang, Chao Wang, Xuehai Zhou. 332-338 [doi]
• DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative ModelXuanzheng Wang, Shuo Miao, Peng Qu, Youhui Zhang. 339-345 [doi]
• CFSA: An Efficient CPU-FPGA Synergies Accelerator for Neural Radiation Field RenderingShangrong Li, Kai Liu, Wei Liu, Zibo Guo. 346-352 [doi]