Table of Contents

• Rapid RTL-based signal ranking for FPGA prototypingSteven J. E. Wilton, Bradley R. Quinton, Eddie Hung. 1-7 [doi]
• K-way partitioning based packing for FPGA logic blocks without input bandwidth constraintWenyi Feng. 8-15 [doi]
• Neural network based pre-placement wirelength estimationQiang Liu, Jianguo Ma, Qijun Zhang. 16-22 [doi]
• Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAsJu-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He. 23-28 [doi]
• FPGA based memory efficient high resolution stereo vision system for video tollingYi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang 0002, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang. 29-32 [doi]
• A task-level OoO framework for heterogeneous systemsJunneng Zhang, Chao Wang, Xi Li, Peng Chen 0004, Xiaojing Feng, Xuehai Zhou. 33-36 [doi]
• FPGA-GPU-CPU heterogenous architecture for real-time cardiac physiological optical mappingPingfan Meng, Matthew Jacobsen, Ryan Kastner. 37-42 [doi]
• Managing mutex variables in a cache-coherent shared-memory system for FPGAsVincent Mirian, Paul Chow. 43-46 [doi]
• FPGA optimized packet-switched NoC using split and merge primitivesYutian Huan, André DeHon. 47-52 [doi]
• Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCsChao Wang, Xi Li, Xuehai Zhou, Yajun Ha. 53-56 [doi]
• Guppy: A GPU-like soft-core processorAbdullah Al-Dujaili, Florian Deragisch, Andrei Hagiescu, Weng-Fai Wong. 57-60 [doi]
• A high speed open source controller for FPGA Partial ReconfigurationKizheppatt Vipin, Suhaib A. Fahmy. 61-66 [doi]
• Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable ProcessorDongkwan Suh, Kiseok Kwon, Sukjin Kim, Soojung Ryu, Jeongwook Kim. 67-70 [doi]
• Small virtual channel routers on FPGAs through block RAM sharingJimmy Kwa, Tor M. Aamodt. 71-79 [doi]
• uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodologyYi-Chung Chen, Wenhua Wang, Wei Zhang, Hai Li. 80-86 [doi]
• An FPGA with power-gated switch blocksAssem A. M. Bsoul, Steven J. E. Wilton. 87-94 [doi]
• Design tradeoffs for hard and soft FPGA-based Networks-on-ChipMohamed S. Abdelfattah, Vaughn Betz. 95-103 [doi]
• Rule-based data communication optimization using quantitative communication profilingCuong Pham-Quoc, Zaid Al-Ars, Koen Bertels. 104-108 [doi]
• Parametric reconfigurable designs with Machine Learning OptimizerMaciej Kurek, Wayne Luk. 109-112 [doi]
• Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modulesBenjamin Y. Brewster, Ekawat Homsirikamol, Rajesh Velegalati, Kris Gaj. 113-118 [doi]
• A study of adaptable co-processors for Cyclic Redundancy Check on an FPGAAmila Akagic, Hideharu Amano. 119-124 [doi]
• Side-channel resistant AES architecture utilizing randomized composite field representationsBernhard Jungk, Marc Stöttinger, Jan Gampe, Steffen Reith, Sorin A. Huss. 125-128 [doi]
• Resiliency-aware scheduling: Resource allocation for hardened computation on configurable devicesJeremy Abramson, Pedro C. Diniz. 129-134 [doi]
• FPGA-based design and implementation of an approximate polynomial matrix EVD algorithmServer Kasap, Soydan Redif. 135-140 [doi]
• Automatic rectification of design errors in complex processors with programmable hardwareAmir Masoud Gharehbaghi, Masahiro Fujita. 141-146 [doi]
• Verification of streaming hardware and software codesignsTim Todman, Peter Boehm, Wayne Luk. 147-150 [doi]
• iDEA: A DSP block based FPGA soft processorHui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell. 151-158 [doi]
• A memory-efficient parallel single pass architecture for connected component labeling of streamed imagesMichael Klaiber, Lars Rockstroh, Zhe Wang, Yousef Baroud, Sven Simon. 159-165 [doi]
• An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detectionBraiden Brousseau, Jonathan Rose. 166-173 [doi]
• A high-performance architecture for training Viola-Jones object detectorsCharles Lo, Paul Chow. 174-181 [doi]
• A fully-pipelined expectation-maximization engine for Gaussian Mixture ModelsCe Guo, Haohuan Fu, Wayne Luk. 182-189 [doi]
• Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python methodYuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei. 190-197 [doi]
• Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPUJunying Chen, Alfred C. H. Yu, Hayden Kwok-Hay So. 198-205 [doi]
• Designing a hardware in the loop wireless digital channel emulator for software defined radioJanarbek Matai, Pingfan Meng, Lingjuan Wu, Brad T. Weals, Ryan Kastner. 206-214 [doi]
• Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAsAbdulazim Amouri, Saman Kiamehr, Mehdi Baradaran Tahoori. 215-219 [doi]
• Accelerated evaluation of SEU failure-in-time using frame-based partial reconfigurationYoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi. 220-223 [doi]
• Introducing irregularity to routing architecture of structured ASIC for better routabilityInsup Shin, Donkyu Baek, Youngsoo Shin. 224-228 [doi]
• VersaPower: Power estimation for diverse FPGA architecturesJeffrey B. Goeders, Steven J. E. Wilton. 229-234 [doi]
• Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skewAlexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux. 235-238 [doi]
• Acceleration of fault attack emulation by consideration of fault propagationArmin Krieg, Johannes Grinschgl, Holger Bock, Josef Haid. 239-242 [doi]
• Implementation of a volume rendering on coarse-grained reconfigurable multiprocessorSeunghun Jin, Sang-Heon Lee, Moo-Kyoung Chung, Yeon Gon Cho, Soojung Ryu. 243-246 [doi]
• Area constraint propagation in high level synthesisRazvan Nane, Vlad Mihai Sima, Koen Bertels. 247-252 [doi]
• A hardware security module for quadrotor communicationAbdulhadi Shoufan. 253-256 [doi]
• A new hardware coprocessor for accelerating Notification-Oriented applicationsEduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean M. Simao. 257-260 [doi]
• VENICE: A compact vector processor for FPGA applicationsAaron Severance, Guy Lemieux. 261-268 [doi]
• A partially reconfigurable architecture supporting hardware threadsYing Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong. 269-276 [doi]
• Software-managed automatic data sharing for Coarse-Grained Reconfigurable coprocessorsToan X. Mai, Jongeun Lee. 277-284 [doi]
• Graph minor approach for application mapping on CGRAsLiang Chen, Tulika Mitra. 285-292 [doi]
• Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnectYusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura. 293-296 [doi]
• Area-time estimation of C-based functions for design space explorationYan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan. 297-300 [doi]
• An island-style-routing compatible fault-tolerant FPGA architecture with self-repairing capabilitiesHasan Baig, Jeong-A. Lee. 301-304 [doi]
• Streamed high dynamic range imagingDonald G. Bailey. 305-308 [doi]
• SimXMD: Integrated debugging of C code and hardware componentsRuediger Willenberg, Paul Chow. 309-312 [doi]
• Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable ArraysHee-Seok Kim, Minwook Ahn, John A. Stratton, Wen-mei W. Hwu. 313-320 [doi]
• SCC based modulo scheduling for coarse-grained reconfigurable processorsWonsub Kim, Donghoon Yoo, Haewoo Park, Minwook Ahn. 321-328 [doi]
• ULP-SRP: Ultra low power Samsung Reconfigurable Processor for biomedical applicationsChangmoo Kim, Moo-Kyoung Chung, Yeon Gon Cho, Mario Konijnenburg, Soojung Ryu, Jeongwook Kim. 329-334 [doi]
• Efficient performance scaling of future CGRAs for mobile applicationsYongjun Park, Jason Jong Kyu Park, Scott A. Mahlke. 335-342 [doi]
• ZIP-IO: Architecture for application-specific compression of Big DataSang-Woo Jun, Kermin Fleming, Michael Adler, Joel S. Emer. 343-351 [doi]
• Parallelizing sparse LU decomposition on FPGAsGuiming Wu, Xianghui Xie, Yong Dou, Junqing Sun, Dong Wu, Yuan Li. 352-359 [doi]
• Minimizing the error: A study of the implementation of an Integer Split-Radix FFT on an FPGA for medical imagingMohammad Reza Mohammadnia, Lesley Shannon. 360-367 [doi]
• Low complexity and hardware-friendly spectral modular multiplicationDonald Donglong Chen, Gavin Xiaoxu Yao, Çetin Kaya Koç, Ray C. C. Cheung. 368-375 [doi]