Abstract is missing.
- Logic emulation in the megaLUT era - Moore's Law beats Rent's RuleMike Butts. 1 [doi]
- Automating customized computingJason Cong. 2 [doi]
- Doing FPGA in a former software companyFeng-hsiung Hsu. 3 [doi]
- Design re-use for compile time reduction in FPGA high-level synthesis flowsMarcel Gort, Jason Helge Anderson. 4-11 [doi]
- Is high level synthesis ready for business? A computational finance case studyGordon Inggs, Shane T. Fleming, David B. Thomas, Wayne Luk. 12-19 [doi]
- Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLSRafat Rashid, J. Gregory Steffan, Vaughn Betz. 20-27 [doi]
- Size aware placement for island style FPGAsJunying Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang. 28-35 [doi]
- Analyzing the impact of heterogeneous blocks on FPGA placement qualityChang Xu, Wentai Zhang, Guojie Luo. 36-43 [doi]
- Low-latency option pricing using systolic binomial treesAryan Tavakkoli, David B. Thomas. 44-51 [doi]
- Collaborative processing of Least-Square Monte Carlo for American optionsJinzhe Yang, Ce Guo, Wayne Luk, Terence Nahar. 52-59 [doi]
- Accelerating transfer entropy computationShengjia Shao, Ce Guo, Wayne Luk, Stephen Weston. 60-67 [doi]
- FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridgesMark de Jong, Vlad Mihai Sima, Koen Bertels, David Thomas. 68-75 [doi]
- Time sharing of Runtime Coarse-Grain Reconfigurable Architectures processing elements in multi-process systemsBenjamin Carrión Schafer. 76-82 [doi]
- Architectural synthesis of computational pipelines with decoupled memory accessShaoyi Cheng, John Wawrzynek. 83-90 [doi]
- Improve memory access for achieving both performance and energy efficiencies on heterogeneous systemsHongyuan Ding, Miaoqing Huang. 91-98 [doi]
- Approaching overhead-free execution on FPGA soft-processorsCharles Eric LaForest, Jason Helge Anderson, J. Gregory Steffan. 99-106 [doi]
- Low-latency double-precision floating-point division for FPGAsBjörn Liebig, Andreas Koch 0001. 107-114 [doi]
- Efficient FPGA implementation of digit parallel online arithmetic operatorsKan Shi, David Boland, George A. Constantinides. 115-122 [doi]
- An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDICJianfeng Zhang, Paul Chow, Hengzhu Liu. 123-130 [doi]
- Area efficient floating-point adder and multiplier with IEEE-754 compatible semanticsAndreas Ehliar. 131-138 [doi]
- A universal FPGA-based floating-point matrix processor for mobile systemsWenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma, Yu Wang. 139-146 [doi]
- A survey on security and trust of FPGA-based systemsJiliang Zhang, Gang Qu. 147-152 [doi]
- Hardware Trojan detection acceleration based on word-level statistical properties managementHe Li, Qiang Liu. 153-160 [doi]
- Power supply noise aware evaluation framework for side channel attacks and countermeasuresJianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou. 161-166 [doi]
- Memory security in reconfigurable computers: Combining formal verification with monitoringTobias Wiersema, Stephanie Drzevitzky, Marco Platzner. 167-174 [doi]
- An FPGA-based spectral anomaly detection systemDuncan J. M. Moss, Zhe Zhang, Nicholas J. Fraser, Philip H. W. Leong. 175-182 [doi]
- RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacksAlbert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith, André DeHon. 183-190 [doi]
- Parallel resampling for particle filters on FPGAsShuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis. 191-198 [doi]
- Evaluation of SNMP-like protocol to manage a NoC emulation platformOtavio Alcantara de Lima Junior, Virginie Fresse, Frédéric Rousseau. 199-206 [doi]
- A high-performance low-power near-Vt RRAM-based FPGAXifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 207-214 [doi]
- A pure-CMOS nonvolatile multi-context configuration memory for dynamically reconfigurable FPGAsKosuke Tatsumura, Masato Oda, Shinichi Yasuda. 215-222 [doi]
- A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualizationOliver Sander, Steffen Baehr, Enno Lübbers, Timo Sandmann, Viet Vu Duy, Jürgen Becker. 223-226 [doi]
- Gigabyte-scale alignment acceleration of biological sequences via Ethernet streamingTheepan Moorthy, Sathish Gopalakrishnan. 227-230 [doi]
- Power modelling and capping for heterogeneous ARM/FPGA SoCsYun Wu, José L. Núñez-Yáñez, Roger Woods, Dimitrios S. Nikolopoulos. 231-234 [doi]
- Analysis and optimization of a deeply pipelined FPGA soft processorHui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre. 235-238 [doi]
- A circuit to synchronize high speed serial communication channelMrinal J. Sarmah, Syed Azeemuddin. 239-242 [doi]
- Novel reconfigurable hardware implementation of polynomial matrix/vector multiplicationsServer Kasap, Soydan Redif. 243-247 [doi]
- A complementary architecture for high-speed true random number generatorXian Yang, Ray C. C. Cheung. 248-251 [doi]
- Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorizationSiddhartha, Nachiket Kapre. 252-255 [doi]
- Zero latency encryption with FPGAs for secure time-triggered automotive networksShanker Shreejith, Suhaib A. Fahmy. 256-259 [doi]
- Using C to implement high-efficient computation of dense optical flow on FPGA-accelerated heterogeneous platformsZhiLei Chai, Haojie Zhou, Zhibin Wang, Dong Wu. 260-263 [doi]
- Hardware architecture of bi-cubic convolution interpolation for real-time image scalingGopinath Mahale, Hamsika Mahale, Rajesh Babu Parimi, S. K. Nandy, S. Bhattacharya. 264-267 [doi]
- FPGA-based high throughput XTS-AES encryption/decryption for storage area networkYi Wang 0016, Akash Kumar, Yajun Ha. 268-271 [doi]
- Zyndroid: An Android platform for software/hardware coprocessingSusumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 272-275 [doi]
- A dataflow system for anomaly detection and analysisAndrei Bara, Xinyu Niu, Wayne Luk. 276-279 [doi]
- Design space exploration for FPGA-based hybrid multicore architectureJian Yan, Junqi Yuan, Ying Wang, Philip Leong, Lingli Wang. 280-281 [doi]
- Reducing the overhead of dynamic partial reconfiguration for multi-mode circuitsBrahim Al Farisi, Karel Heyse, Dirk Stroobandt. 282-283 [doi]
- HW acceleration of multiple applications on a single FPGAYidi Liu, Benjamin Carrión Schäfer. 284-285 [doi]
- Towards automatic partial reconfiguration in FPGAsFubing Mao, Wei Zhang, Bingsheng He. 286-287 [doi]
- Achieving higher performance of memcached by caching at network interfaceEric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura. 288-289 [doi]
- No zero padded sparse matrix-vector multiplication on FPGAsJiasen Huang, Junyan Ren, Wenbo Yin, Lingli Wang. 290-291 [doi]
- AMMC: Advanced Multi-Core Memory ControllerTassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal. 292-295 [doi]
- Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applicationsFredrik Brosser, Emil Milh, Vilhelm Geijer, Per Larsson-Edefors. 296-299 [doi]
- A fast, energy efficient, field programmable threshold-logic arrayNiranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula. 300-305 [doi]
- A novel three-dimensional FPGA architecture with high-speed serial communication linksTakuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi. 306-309 [doi]
- Scalable radio processor architecture for modern wireless communicationsYoung-Hwan Park, Keshava Prasad, Yeonbok Lee, Kitaek Bae, Ho Yang. 310-313 [doi]
- Integrating FPGA-based processing elements into a runtime for parallel heterogeneous computingDavid de la Chevallerie, Jens Korinth, Andreas Koch. 314-317 [doi]
- Deep and narrow binary content-addressable memories using FPGA-based BRAMsAmeer M. S. Abdelhadi, Guy G. F. Lemieux. 318-321 [doi]
- Development productivity in implementing a complex heterogeneous computing applicationAnthony Milton, David A. Kearney, Sebastien C. Wong, Simon Lemmo. 322-325 [doi]
- Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDKQuentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner. 326-329 [doi]
- Online scheduling for FPGA computation in the CloudGuohao Dai, Yi Shan, Fei Chen, Yu Wang, Kun Wang, Huazhong Yang. 330-333 [doi]
- High performance relevance vector machine on HMPSoCYongfu He, Shaojun Wang, Yu Peng, Yeyong Pang, Ning Ma, Jingyue Pang. 334-337 [doi]
- Improving the reliability of RO PUF using frequency offsetBin Tang, Yaping Lin, Jiliang Zhang. 338-341 [doi]
- Network recorder and player: FPGA-based network traffic capture and replaySiyi Qiao, Chen Xu, Lei Xie, Ji Yang, Chengchen Hu, Xiaohong Guan, Jianhua Zou. 342-345 [doi]
- Implementation of LS-SVM with HLS on ZynqNing Ma, Shaojun Wang, Yeyong Pang, Yu Peng. 346-349 [doi]
- A high-performance and high-programmability reconfigurable wireless development platformJiahua Chen, Tao Wang, Haoyang Wu, Jian Gong, Xiaoguang Li, Yang Hu, Gaohan Zhang, Zhiwei Li, Junrui Yang, Songwu Lu. 350-353 [doi]
- Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar batteryYu Fujita, Koichiro Masuyama, Hideharu Amano. 354-357 [doi]
- Hardware/software co-design architecture for Blokus Duo solverNaru Sugimoto, Hideharu Amano. 358-361 [doi]
- Optimize MinMax algorithm to solve Blokus Duo game by HDLHossein Borhanifar, Seyed Peyman Zolnouri. 362-365 [doi]
- An improved FPGA-based specific processor for Blokus DuoJavier Olivito, Alberto Delmas, Javier Resano. 366-369 [doi]
- Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGAEhsan Qasemi, Amir Samadi, Mohammad H. Shadmehr, Bardia Azizian, Sajjad Mozaffari, Amir Shirian, Bijan Alizadeh. 370-373 [doi]
- Blokus Duo engine on a ZynqSusumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 374-377 [doi]
- FPGA implementation of Blokus Duo player using hardware/software co-designAkira Kojima. 378-381 [doi]