Abstract is missing.
- RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGAKaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano. 1-9 [doi]
- Performance Evaluation on GPU-FPGA Accelerated Computing Considering Interconnections between AcceleratorsYuka Sano, Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku. 10-16 [doi]
- Verifying Hardware Optimizations for Efficient AccelerationQianzhou Wang, Yat Wong, Zhiqiang Que, Wayne Luk. 17-23 [doi]
- Accelerating Decision Tree Ensemble with Guided Branch ApproximationKeisuke Kamahori, Shinya Takamaeda-Yamazaki. 24-32 [doi]
- A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware acceleratorsChristian Maximilian Karle, Marius Kreutzer, Johannes Pfau, Jürgen Becker 0001. 33-41 [doi]
- Meta-Programming Design-Flow Patterns for Automating Reusable OptimisationsJessica Vandebon, José Gabriel F. Coutinho, Wayne Luk. 42-50 [doi]
- A single-source C++20 HLS flow for function evaluation on FPGA and beyondLuc Forget, Gauthier Harnisch, Ronan Keryell, Florent de Dinechin. 51-58 [doi]
- Memory and Energy Efficient Memory Model and Instruction Set Architectures for Tree Data StructuresMouad Rifai, Lennart Johnsson. 59-68 [doi]
- Stream Computation of 3D Approximate Convex Hulls with an FPGATatsuma Mori, Daiki Furukawa, Keigo Motoyoshi, Haruto Ikehara, Kaito Ohira, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano. 69-75 [doi]
- Hash Distributed A* on an FPGARyuichi Sakamoto, Yuriko Ezaki, Masaaki Kondo. 76-83 [doi]
- Non-deterministic event brokered computingAndrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev. 84-86 [doi]
- A Novel Scalable Decision Tree Implementation on SoC Based FPGAsMostafa Koraei, Petter Lefoka. 87-89 [doi]
- FPGA-Dedicated Network vs. Server Network for Pipelined Computing with Multiple FPGAsTomohiro Ueno, Takaaki Miyajima, Kentaro Sano. 90-91 [doi]
- A SYCL-based high-level programming framework for HPC programmers to use remote FPGA clustersSatoshi Kaneko, Hiroyuki Takizawa, Kentaro Sano. 92-94 [doi]
- Low-power option Greeks: Efficiency-driven market risk analysis using FPGAsMark Klaisoongnoen, Nick Brown 0002, Oliver Thomson Brown. 95-101 [doi]
- Very Low Power High-Frequency Floating Point FPGA PID ControllerRadhit Dedania, Sang-Woo Jun. 102-107 [doi]
- Object Detection and Tracking using CouNT and Motion Vectors on FPGAYoshiki Kunimoto, Tsutomu Maruyama. 108-111 [doi]
- Artificial Resilience in neuromorphic systemsAlessio Carpegna, Stefano Di Carlo, Alessandro Savino. 112-114 [doi]