Abstract is missing.
- Supercomputing for the Future, Supercomputing from the Past (Keynote)Mateo Valero, Jesús Labarta. 3-5 [doi]
- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time ProcessingKevin D. Kissell. 9-21 [doi]
- rMPI: Message Passing on Multicore Processors with On-Chip InterconnectJames Psota, Anant Agarwal. 22-37 [doi]
- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BEFilip Blagojevic, Xizhou Feng, Kirk W. Cameron, Dimitrios S. Nikolopoulos. 38-52 [doi]
- BRAM-LUT Tradeoff on a Polymorphic DES DesignRicardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis. 55-65 [doi]
- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable ArrayFrank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev. 66-81 [doi]
- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIPJochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen. 82-96 [doi]
- Fast Bounds Checking Using Debug RegisterTzi-cker Chiueh. 99-113 [doi]
- Studying Compiler Optimizations on Superscalar Processors Through Interval AnalysisStijn Eyerman, Lieven Eeckhout, James E. Smith. 114-129 [doi]
- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded SystemsMarco Cornero, Roberto Costa, Ricardo Fernández Pascual, Andrea C. Ornstein, Erven Rohou. 130-144 [doi]
- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length InstructionsTodd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal. 147-160 [doi]
- Experiences with Parallelizing a Bio-informatics Program on the Cell BEHans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere. 161-175 [doi]
- Drug Design Issues on the Cell BEHarald Servat, Cecilia González-Alvarez, Xavier Aguilar, Daniel Cabrera-Benitez, Daniel Jiménez-González. 176-190 [doi]
- Coffee: COmpiler Framework for Energy-Aware ExplorationPraveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest. 193-208 [doi]
- Integrated CPU Cache Power Management in Multiple Clock Domain ProcessorsNevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem. 209-223 [doi]
- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process VariationMaziar Goudarzi, Tohru Ishihara, Hamid Noori. 224-239 [doi]
- The Significance of Affectors and Affectees Correlations for Branch PredictionYiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous. 243-257 [doi]
- Turbo-ROB: A Low Cost Checkpoint/Restore AcceleratorPatrick Akl, Andreas Moshovos. 258-272 [doi]
- LPA: A First Approach to the Loop Processor ArchitectureAlejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero. 273-287 [doi]
- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation AlgorithmRoy Levin, Ilan Newman, Gadi Haber. 291-304 [doi]
- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and AccuracyVincent M. Weaver, Sally A. McKee. 305-319 [doi]
- Phase Complexity Surfaces: Characterizing Time-Varying Program BehaviorFrederik Vandeputte, Lieven Eeckhout. 320-334 [doi]
- MLP-Aware Dynamic Cache PartitioningMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. 337-352 [doi]
- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded ArchitectureSubhradyuti Sarkar, Dean M. Tullsen. 353-368 [doi]
- Code Arrangement of Embedded Java Virtual Machine for NAND Flash MemoryChun-Chieh Lin, Chuen-Liang Chen. 369-383 [doi]
- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction CacheYosi Ben-Asher, Omer Boehm, Daniel Citron, Gadi Haber, Moshe Klausner, Roy Levin, Yousef Shajrawi. 384-397 [doi]