Abstract is missing.
- Nano, quantum, and molecular computing: are we ready for the validation and test challenges?Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu. 3-7 [doi]
- Software-based self-test methodology for crosstalk faults in processorsXiaoliang Bai, Li Chen, Sujit Dey. 11-16 [doi]
- FPgen - a test generation framework for datapath floating-point verificationMerav Aharoni, Sigal Asaf, Laurent Fournier, Anatoly Koyfman, Raviv Nagel. 17-22 [doi]
- Piparazzi: a test program generator for micro-architecture flow verificationAllon Adir, Eyal Bin, Ofer Peled, Avi Ziv. 23-28 [doi]
- Automatic functional verification of memory oriented global source code transformationsK. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens. 31-36 [doi]
- Refactoring digital hardware designs with assertion librariesFlávio Miana de Paula, Claudionor José Nunes Coelho Jr., Harry Foster, José Augusto Miranda Nacif, Joseph Tompkins, Antônio Otávio Fernandes, Diogenes C. da Silva Jr.. 37-42 [doi]
- High-level optimization of pipeline designJennifer Campbell, Nancy A. Day. 43-48 [doi]
- Integrating CNF and BDD based SAT solversSivaram Gopalakrishnan, Vijay Durairaj, Priyank Kalla. 51-56 [doi]
- Logic transformation and coding theory-based frameworks for Boolean satisfiabilityDhiraj K. Pradhan. 57-62 [doi]
- Enhancing SAT-based equivalence checking with static logic implicationsRajat Arora, Michael S. Hsiao. 63-68 [doi]
- Relating vehicle-level and network-level reliability through high-level fault injectionFulvio Corno, Paolo Gabrielli, Simonluca Tosato. 71-76 [doi]
- Testing ThumbPod: Softcore bugs are hard to findPatrick Schaumont, Kazuo Sakiyama, Yi Fan, David D. Hwang, Shenglin Yang, Alireza Hodjat, Bo-Cheng Lai, Ingrid Verbauwhede. 77-82 [doi]
- Verifying LOC based functional and performance constraintsXi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe. 83-88 [doi]
- Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verificationMarkus Braun, Wolfgang Rosenstiel, Klaus-Dieter Schubert. 91-95 [doi]
- Enhancing the control and efficiency of the covering process [logic verification]Shai Fine, Avi Ziv. 96-101 [doi]
- Functional vector generation for assertion-based verification at behavioral level using interval analysisIñigo Ugarte, Pablo Sanchez. 102-107 [doi]
- Redundant functional faults reduction by saboteurs synthesis [logic verification]Franco Fummi, Cristina Marconcini, Graziano Pravadelli. 108-113 [doi]
- ATPG-based preimage computation: efficient search space pruning with ZBDDKameshwar Chandrasekar, Michael S. Hsiao. 117-122 [doi]
- BDD-based verification of scalable designsDaniel Große, Rolf Drechsler. 123-128 [doi]
- Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checkingSolaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jérôme Rampon. 129-134 [doi]
- Mathematical framework for representing discrete functions as word-level polynomialsDhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski. 135-139 [doi]
- High-level test generation for hardware testing and software validationOlga Goloubeva, Matteo Sonza Reorda, Massimo Violante. 143-148 [doi]
- Scheduling of transactions for system-level test-case generationRoy Emek, Yehuda Naveh. 149-154 [doi]
- A comparison of BDDs, BMC, and sequential SAT for model checkingGanapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang. 157-162 [doi]
- Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?Alessandro Fin, Franco Fummi. 163-168 [doi]
- A method for the evaluation of behavioral fault modelsEmilio Gaudette, Michael Moussa, Ian G. Harris. 169-172 [doi]
- Panel: What's the next 'big thing' in simulation-based verification?Moshe Levinger, Avi Ziv, Brian Bailey, J. Abraham, William H. Joyner, Yaron Kas. 175 [doi]