Table of Contents

• The MIPS32® 34K processor: Ultimate design flexibility for embedded applicationsRyan Kinter. 1-21 [doi]
• Wireless in the home - opportunities and challengesJan M. Rabaey. 1-134 [doi]
• Multithreaded programming challenges, current practice, and languages/tools supportYuan Lin. 1-134 [doi]
• The ultra small HDD for the mobile applicationsAkihiko Takeo, Kazuhito Shimomura, Jun Itoh. 1-22 [doi]
• An implementation of hardware accelerator using dynamically reconfigurable architectureTakashi Yoshikawa, Yutaka Yamada, Shigehiro Asano. 1-38 [doi]
• The CA1024: A fully programmable system-on-chip for costeffective HDTV media processingLazar Bivolarski, Bogdan Mitu, Anand Sheel, Gheorghe Stefan, Tom Thomson, Dan Tomescu. 1-26 [doi]
• Niagara-2: A highly threaded server-on-a-chipGreg Grohoski. 1-22 [doi]
• Who owns the living room?Q. Yamada. 1-8 [doi]
• Software transactional memoryBratin Saha. 1-22 [doi]
• SH-MobileG1: A single-chip application and dual-mode baseband processorMasayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka, Koji Ohno. 1-24 [doi]
• Transactional memory introductionAli-Reza Adl-Tabatabai. 1-21 [doi]
• ARM996HS™ the first licensable, clockless 32-bit processor coreArjan Bink, Richard York. 1-28 [doi]
• Cool codes for hot chips: A quantitative basis for multi-core designJustin Rattner. 1-28 [doi]
• A novel processor architecture for high-performance stream processingJan van Lunteren. 1-24 [doi]
• The APP300 access network processorBalakrishnan Sundararaman. 1-29 [doi]
• Hot chips 18 industry panel: Who owns the living room?James Akiyama. 1-5 [doi]
• Research accelerator for multiple processorsDavid A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek. 1-42 [doi]
• Who owns the living room?Bill Curtis. 1-8 [doi]
• Home entertainment-quality multimedia experience whilst on the moveMarcin Klecha, Ralf Karge, Richard O'Connor. 1-22 [doi]
• Hardware and applications of AsAP: An asynchronous array of simple processorsBevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin. 1-31 [doi]
• Inside Intel® Core microarchitectureJack Doweck. 1-35 [doi]
• A low-latency, high-bandwidth ethernet switch chipUri Cummings. 1-26 [doi]
• Design of a reusable 1GHz, superscalar ARM processorStephen Hill. 1-18 [doi]
• Blackford: A duall processor chipset for servers and workstatiionsKai Cheng, Sundaram Chinthamani, Sivakumar Radhakrishnan, Faye A. Briggs, Kathy Debnath. 1-28 [doi]
• Who owns the living room?Glen Stone. 1-6 [doi]
• TeraOPS hardware: A new massively-parallel MIMD computing fabric ICAnthony Mark Jones, Mike Butts. 1-15 [doi]
• Z-RAM® ultra-dense memory for 90nm and belowDavid E. Fisch, Anant Singh, Greg Popov. 1-35 [doi]
• The next generation 65-nm FPGASteve Douglass, Kees A. Vissers, Peter Alfke. 1-27 [doi]
• Transactional memory implementation overviewChristos Kozyrakis. 1-31 [doi]
• Who owns the living room?Alan Messer. 1-6 [doi]
• Microsoft microsoft in the living roomBob Brummer. 1-5 [doi]
• Micro manipulator array for nano-bioelectronics eraK. Suzuki, Y. Naruse, Hideyuki Funaki, Kazuhiko Itaya, S. Uchikoga. 1-27 [doi]
• The tulsa processor: A dual core large shared-cache Intel® Xeon processor 7000 sequence for the MP server market segmentJeffrey D. Gilbert, Stephen H. Hunt, Daniel Gunadi, Ganapati Srinivas. 1-38 [doi]
• Collaborative innovation; a new lever in information technology developmentBernard S. Meyerson. 1-27 [doi]
• The AMD Opteron™ CMP NorthBridge architecture: Now and in the futurePat Conway, Bill Hughes. 1-30 [doi]
• PNX8535 hybrid television processorBen J. Pronk. 1-22 [doi]
• Low-power, high-performance architecture of the PWRficient processor familyTse-Yu Yeh. 1-29 [doi]
• In silico vox: Towards speech recognition in siliconEdward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen. 1-27 [doi]
• Towards optimal custom instruction processorsWayne Luk, Kubilay Atasu, Robert G. Dimond, Oskar Mencer. 1-23 [doi]