Yutaka Yamada - researchr alias

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Viewing Publication 1 - 16 from 16

2022

Trend Prediction of Students' Mock Examination Results Using Matrix CompletionYutaka Yamada, Keisuke Maeda, Takahiro Ogawa 0001, Miki Haseyama. gcce 2022: 891-892 [doi]

2020

2019

2015

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applicationsJun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori. isscc 2015: 1-3 [doi]

2011

Virtual Screening for Ligands of the Insect Molting Hormone ReceptorToshiyuki Harada, Yoshiaki Nakagawa, Takehiko Ogura, Yutaka Yamada, Takehiro Ohe, Hisashi Miyagawa. jcisd, 51(2):296-305, 2011. [doi]

FlexGrip™: A small and high-performance programmable hardware for highly sequential applicationTakashi Yoshikawa, Fumihiko Hyuga, Masayuki Tokunaga, Yutaka Yamada, Shigehiro Asano. coolchips 2011: 1-3 [doi]

2009

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip NetworkHiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano. tpds, 20(8):1126-1141, 2009. [doi]

2006

A Simple Data Transfer Technique Using Local Address for Networks-on-ChipsMichihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano. tpds, 17(12):1425-1437, 2006. [doi]

An implementation of hardware accelerator using dynamically reconfigurable architectureTakashi Yoshikawa, Yutaka Yamada, Shigehiro Asano. hotchips 2006: 1-38 [doi]

2005

Evaluation of vibration in many positions by SOMNobuaki Kamimoto, Yutaka Yamada, Masami Kitamura, Kiyoshi Nishikawa. alr, 9(1):7-11, 2005. [doi]

Non-Minimal Routing Strategy for Application-Specific Networks-on-ChipsHiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano. icppw 2005: 273-280 [doi]

2004

BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-ChipsKenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano. ipps 2004: [doi]

Stream applications on the dynamically reconfigurable processorMasayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima. fpt 2004: 137-144 [doi]

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable ProcessorNoriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima. fccm 2004: 328-329 [doi]

Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor ArrayYutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura. euc 2004: 301-311 [doi]

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