Abstract is missing.
- Programming a hyper-programmable architecture for networked systemsEric Keller, Gordon J. Brebner. 1-8 [doi]
- Self-recovery experiments in extreme environments using a field programmable transistor arrayAdrian Stoica, Didier Keymeulen, Tughrul Arslan, Vu Duong, Ricardo Salem Zebulum, Ian Ferguson, Xin Guo. 9-15 [doi]
- Field programmable gate array implementation of a generalized decoder for structured low-density parity check codesLingyan Sun, B. V. K. Vijaya Kumar. 17-24 [doi]
- Partial character decoding for improved regular expression matching in FPGAsPeter Sutton. 25-32 [doi]
- Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arraysSteven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde. 33-40 [doi]
- Directional and single-driver wires in FPGA interconnectGuy Lemieux, Edmund Lee 0002, Marvin Tom, Anthony J. Yu. 41-48 [doi]
- A greedy algorithm for tolerating defective crosspoints in nanoPLA designHelia Naeimi, André DeHon. 49-56 [doi]
- SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysisR. Manimegalai, B. Jayaram, A. Manoj Kumar, V. Kamakoti. 57-64 [doi]
- Placement and routing for non-rectangular embedded programmable logic cores in SoC designTony Wong, Steven J. E. Wilton. 65-72 [doi]
- QuickRoute: a fast routing algorithm for pipelined architecturesSong Li, Carl Ebeling. 73-80 [doi]
- An FPGA-based Othello endgame solverC. K. Wong, K. K. Lo, P. H. W. Leong. 81-88 [doi]
- Real-time detection of line segments using the line Hough transformNozomu Nagata, Tsutomu Maruyama. 89-96 [doi]
- gNBX - reconfigurable hardware acceleration of self-organizing mapsChristopher Pohl, Marc Franzmeier, Mario Porrmann, Ulrich Rückert. 97-104 [doi]
- Evolvability and reconfigurabilityCristina Costa Santini, José F. M. do Amaral, Marco Aurélio Cavalcanti Pacheco, Ricardo Tanscheit. 105-112 [doi]
- A gate-level model for morphogenetic evolvable hardwareJustin Lee, Joaquin Sitte. 113-119 [doi]
- A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAsE. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan. 121-128 [doi]
- Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuitsAndy Gean Ye, Jonathan Rose. 129-136 [doi]
- Stream applications on the dynamically reconfigurable processorMasayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima. 137-144 [doi]
- Compiler reuse analysis for the mapping of data in FPGAs with RAM blocksNastaran Baradaran, Joonseok Park, Pedro C. Diniz. 145-152 [doi]
- Memory optimisations for high-resolution imagingTim Todman, Wayne Luk. 153-160 [doi]
- On the placement and granularity of FPGA configurationsUsama Malik, Oliver Diessel. 161-168 [doi]
- Adaptive range reduction for hardware function evaluationDong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk. 169-176 [doi]
- A scalable hardware architecture for prime number validationRay C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung. 177-184 [doi]
- Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplicationMáire McLoone, Ciaran McIvor, John V. McCanny. 185-191 [doi]
- Programmable parallel coprocessor architectures for reconfigurable system-on-chipJohn Williams, Neil W. Bergmann. 193-200 [doi]
- Windows CE for a reconfigurable system-on-a-chip processorMariam Reeny George, Weng-Fai Wong. 201-207 [doi]
- EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGAHidetomo Shibamura, Masayuki Fukuyama, Daisuke Uchida, Seiji Ikeda, Morihiro Kuga, Toshinori Sueyoshi. 209-216 [doi]
- Migrating software to hardware on FPGAsRussell Klein, Rajat Moona. 217-224 [doi]
- The Quartus University Interface Program: enabling advanced FPGA researchShawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown. 225-230 [doi]
- Maximizing system performance: using reconfigurability to monitor system communicationsLesley Shannon, Paul Chow. 231-238 [doi]
- Using function folding to improve silicon efficiency of reconfigurable arithmetic arraysMarkus Weinhardt, Martin Vorbach, Volker Baumgarten, Frank May. 239-245 [doi]
- Low FPGA area multiplier blocks for full parallel FIR filtersKenneth N. Macpherson, Robert W. Stewart. 247-254 [doi]
- Pipelining designs with loop-carried dependenciesHenry Styles, David B. Thomas, Wayne Luk. 255-262 [doi]
- Reconfigurable hardware implementation of mesh routing in number field sieve factorizationSashisu Bajracharya, Deapesh Misra, Kris Gaj, Tarek A. El-Ghazawi. 263-270 [doi]
- Fast architectures for FPGA-based implementation of RSA encryption algorithmOmar Nibouche, Mokhtar Nibouche, Ahmed Bouridane, Ammar Belatreche. 271-278 [doi]
- Single-chip FPGA implementation of a cryptographic co-processorFrancis M. Crowe, Alan Daly, Tim Kerins, William P. Marnane. 279-285 [doi]
- m) for two classes of finite fieldsJosé Luis Imaña. 287-290 [doi]
- Extended genetic algorithm for codesign optimization of DSP systems in FPGAsMatthew J. W. Savage, Zoran A. Salcic, George G. Coghill, Grant Covic. 291-294 [doi]
- FPGA implementation of hierarchical memory architecture for network processorsZhen Liu, Kai Zheng, Bin Liu 0001. 295-298 [doi]
- Evaluating software and hardware implementations of signal-processing tasks in an FPGAPeter Waldeck, Neil W. Bergmann. 299-302 [doi]
- A scalable architecture for elliptic curve point multiplicationKimmo Järvinen, Matti Tommiska, Jorma Skyttä. 303-306 [doi]
- An FPGA based prototyping platform for imager-on-chip applicationsCade C. Wells, Ed Duncan, David Renshaw. 307-310 [doi]
- Compact iterative FPGA Camellia algorithm implementationsDaniel Denning, James Irvine, Malachy Devlin. 311-314 [doi]
- An adaptive Viterbi decoder based on FPGA dynamic reconfiguration technologyXiang-Ju Qin, Ming-Cheng Zhu, Zhong-Yi Wei, Du Chao. 315-318 [doi]
- Single bit error correction implementation in CRC-16 on FPGASunil Shukla, Neil W. Bergmann. 319-322 [doi]
- Pre-silicon prototyping of a unified hardware architecture for cryptographic manipulation detection codesT. S. Ganesh, T. S. B. Sudarshan, Naveen Kumar Srinivasan, Karthick Jayapal. 323-326 [doi]
- FPGA-acceleration of cone-beam reconstruction for the X-ray CTDzmitry Stsepankou, Klaus Kornmesser, Jürgen Hesser, Reinhard Männer. 327-330 [doi]
- Interface adaptor logic - a new model for interfacing peripherals in IP based designsTien-Lung Lee, Andy Lee, Neil W. Bergmann. 331-334 [doi]
- FPGA implementation of digital upconversion using distributed arithmetic FIR filtersT. Salim, John C. Devlin, Jim Whittington. 335-338 [doi]
- FPGA implementation of a phased array DBF using polyphase filtersT. Salim, John C. Devlin, Jim Whittington. 339-342 [doi]
- FPGA design of HECC coprocessorsGrace Elias, Ali Miri, Tet Hin Yeap. 343-346 [doi]
- A tsume-shogi processor based on reconfigurable hardwareYohei Hori, Tsutomu Maruyama, Kenji Toda. 347-350 [doi]
- An approach to realize time-sharing of flip-flops in time-multiplexed FPGAsMd. Ashfaquzzaman Khan, Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Soichiro Kita, Koji Kotani, Tadahiro Ohmi. 351-354 [doi]
- A parameterizable HandelC divider generator for FPGAs with embedded hardware multipliersJohn Hopf. 355-358 [doi]
- Reconfigurable I/O interface for mobile equipmentsNoriyuki Aibe, Moritoshi Yasunaga. 359-362 [doi]
- Domain specific reconfigurable fabric targeting Viterbi algorithmCheng Zhan, Sami Khawam, Tughrul Arslan. 363-366 [doi]
- A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filtersJoachim Becker, Yiannos Manoli. 367-370 [doi]
- RTOS acceleration on soft-core processors using instruction set customizationJin Zhenyu, Mohit Sindhwani, Thambipillai Srikanthan. 371-374 [doi]
- A rapid prototyping framework for audio signal processing algorithmsNikolaus Voß, Thomas Eisenbach, Bärbel Mertsching. 375-378 [doi]
- Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuitsHisanori Fujisawa, Miyoshi Saito, Masaki Arai, Toshihiro Ozawa, Hideki Yoshizawa. 379-382 [doi]
- Achieving wide frequency range in an analog FPGAErik Schüler, Luigi Carro. 383-386 [doi]
- 3D graphics accelerator platform for mobile devicesJung-Woo Kim, Jae-One Oh, Cheol-Ho Jeong, Jae-Hyun Kim. 387-390 [doi]
- Retiming aware clustering for sequential circuitsMehrdad Eslami Dehkordi, Stephen Dean Brown. 391-394 [doi]
- A scalable and pipelined FPGA implementation of an OC192 WF schedulerAbdallah Merhebi, Otmane Aït Mohamed. 395-398 [doi]
- Wavelet spectral dimension reduction of hyperspectral imagery on a reconfigurable computerEsam El-Araby, Tarek A. El-Ghazawi, Jacqueline Le Moigne, Kris Gaj. 399-402 [doi]
- Architectures for ICT on FPGAArturo Méndez Patiño, Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá. 403-406 [doi]
- Design of an imaging system based on FPGA technology and CMOS imagerPierre Chalimbaud, François Berry. 407-411 [doi]
- Study on column wise design compaction for reconfigurable systemsHeiko Kalte, Gareth Lee, Mario Porrmann, Ulrich Rückert. 413-416 [doi]
- Memory specification for reconfigurable computing synthesis toolsJohn Xue, Peter Sutton. 417-420 [doi]
- Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architectureLodewijk T. Smit, Gerard J. M. Smit, Johann L. Hurink, Hajo Broersma, Daniël Paulusma, Pascal T. Wolkotte. 421-424 [doi]
- An FPGA implementation of a modified version of RED algorithmFariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed. 425-428 [doi]
- A new reconfigurable architecture with smart data-transfer subsystems for the intelligent image processingHiroshi Kadota, Yoshiaki Hori, Akiyoshi Wakatani. 429-432 [doi]
- FPGA architecture extensions for preemptive multitasking and hardware defragmentationDirk Koch, Ali Ahmadinia, Christophe Bobda, Heiko Kalte. 433-436 [doi]
- Implementation of a flexible RAKE receiver in heterogeneous reconfigurable hardwareGerard K. Rauwerda, Gerard J. M. Smit. 437-440 [doi]
- An improved Montgomery modular inversion targeted for efficient implementation on FPGAGuerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater. 441-444 [doi]
- Hardware/software co-simulation environment for CSoC with soft processorsRaúl Mateos, José Luis Lázaro, Felipe Espinosa. 445-448 [doi]
- FPGA implementation of spiking neural networks - an initial step towards building tangible collaborative autonomous agentsStephen J. Bellis, Kafil Mahmood Razeeb, C. R. Saha, Kieran Delaney, S. Cian O'Mathuna, Anthony Pounds-Cornish, Gustavo de Souza, Martin Colley, Hani Hagras, Graham Clarke, Victor Callaghan, Christos Argyropoulos, C. Karistianos, George Nikiforidis. 449-452 [doi]
- Effective system and performance benchmarking for reconfigurable computersEsmail Chitalwala, Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Daniel S. Poznanovic. 453-456 [doi]
- Scalable structured data access by combining autonomous memory blocksWim J. C. Melis, Peter Y. K. Cheung, Wayne Luk. 457-460 [doi]
- An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memoryStephen O'Kane, Sakir Sezer. 461-464 [doi]
- Switch-box design for synthesizable coarse-grain arrays for system-on-chip applicationsSami Khawam, Tughrul Arslan. 465-468 [doi]