Abstract is missing.
- Billion Transistor Chips in Mainstream Enterprise Platforms of the FutureDileep Bhandarkar. 3 [doi]
- Variability in Architectural Simulations of Multi-Threaded WorkloadsAlaa R. Alameldeen, David A. Wood. 7-18 [doi]
- Mini-Threads: Increasing TLP on Small-Scale SMT ProcessorsJoshua Redstone, Susan J. Eggers, Henry M. Levy. 19-30 [doi]
- Front-End Policies for Improved Issue Efficiency in SMT ProcessorsAli El-Moursy, David H. Albonesi. 31 [doi]
- Reconsidering Complex Branch PredictorsDaniel A. Jiménez. 43-52 [doi]
- Incorporating Predicate Information into Branch PredictorsBeth Simon, Brad Calder, Jeanne Ferrante. 53-64 [doi]
- Dynamic Data Dependence Tracking and its Application to Branch PredictionLei Chen, Steve Dropsho, David H. Albonesi. 65 [doi]
- Control Techniques to Eliminate Voltage Emergencies in High Performance ProcessorsRuss Joseph, David Brooks, Margaret Martonosi. 79-90 [doi]
- Dynamic Voltage Scaling with Links for Power Optimization of Interconnection NetworksLi Shang, Li-Shiuan Peh, Niraj K. Jha. 91-102 [doi]
- Power-Aware Control Speculation through Selective ThrottlingJuan L. Aragón, José González, Antonio González. 103-112 [doi]
- Deterministic Clock Gating for Microprocessor Power ReductionHai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy. 113 [doi]
- Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order ProcessorsOnur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt. 129-140 [doi]
- Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server SystemsMariko Sakamoto, Akira Katsuno, Aiichiro Inoue, Takeo Asakawa, Haruhiko Ueno, Kuniki Morita, Yasunori Kimura. 141-152 [doi]
- Exploring the VLSI Scalability of Stream ProcessorsBrucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles. 153-164 [doi]
- Dynamic Optimization of Micro-OperationsBrian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta. 165 [doi]
- Slipstream Execution Mode for CMP-Based MultiprocessorsKhaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg. 179-190 [doi]
- Tradeoffs in Buffering Memory State for Thread-Level Speculation in MultiprocessorsMaría Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas. 191-202 [doi]
- Dynamic Data Replication: An Approach to Providing Fault-Tolerant Shared Memory ClustersRosalia Christodoulopoulou, Reza Azimi, Angelos Bilas. 203 [doi]
- Memory System Behavior of Java-Based MiddlewareMartin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood. 217-228 [doi]
- Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based ServicesKiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini, Richard P. Martin, Thu D. Nguyen. 229-240 [doi]
- Hierarchical Backoff Locks for Nonuniform Communication ArchitecturesZoran Radovic, Erik Hagersten. 241-252 [doi]
- Performance Enhancement Techniques for InfiniBand? ArchitectureEun Jung Kim, Ki Hwan Yum, Chita R. Das, Mazin S. Yousif, José Duato. 253 [doi]
- The State of StatePeter M. Kogge. 266 [doi]
- Catching Accurate Profiles in HardwarSatish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, George Varghese. 269-280 [doi]
- A Statistically Rigorous Approach for Improving Simulation MethodologyJoshua J. Yi, David J. Lilja, Douglas M. Hawkins. 281 [doi]
- Caches and Hash Trees for Efficient Memory IntegrityBlaise Gassend, G. Edward Suh, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas. 295-306 [doi]
- Just Say No: Benefits of Early Cache Miss DeterminatioGokhan Memik, Glenn Reinman, William H. Mangione-Smith. 307-316 [doi]
- TCP: Tag Correlating PrefetchersZhigang Hu, Margaret Martonosi, Stefanos Kaxiras. 317-326 [doi]
- Cost-Sensitive Cache Replacement AlgorithmsJaeheon Jeong, Michel Dubois. 327 [doi]
- Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned ArchitectureMichael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal. 341-353 [doi]
- Inter-Cluster Communication Models for Clustered VLIW ProcessorsAndrei Terechko, Erwan Le Thenaff, Manish Garg, Jos T. J. van Eijndhoven, Henk Corporaal. 354-364 [doi]
- Active I/O Switches in System Area NetworksMing Hao, Mark Heinrich. 365-376 [doi]
- A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication PatternsWai Hong Ho, Timothy Mark Pinkston. 377 [doi]