Table of Contents

• Exploring architectural heterogeneity in intelligent vision systemsNandhini Chandramoorthy, Giuseppe Tagliavini, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini. 1-12 [doi]
• BeBoP: A cost effective predictor infrastructure for superscalar value predictionArthur Perais, André Seznec. 13-25 [doi]
• VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessorsTimothy Hayes 0001, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero. 26-38 [doi]
• Increasing multicore system efficiency through intelligent bandwidth shiftingVictor Jiménez, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Francisco J. Cazorla, Mateo Valero. 39-50 [doi]
• Exploiting compressed block size as an indicator of future reuseGennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry. 51-63 [doi]
• Talus: A simple way to remove cliffs in cache performanceNathan Beckmann, Daniel Sanchez. 64-75 [doi]
• Coordinated static and dynamic cache bypassing for GPUsXiaolong Xie, Yun Liang, Yu Wang, Guangyu Sun, Tao Wang. 76-88 [doi]
• Priority-based cache allocation in throughput processorsDong Li, Minsoo Rhu, Daniel R. Johnson, Mike O'Connor, Mattan Erez, Doug Burger, Donald S. Fussell, Stephen W. Redder. 89-100 [doi]
• Bamboo ECC: Strong, safe, and flexible codes for reliable computer memoryJungrae Kim, Michael Sullivan, Mattan Erez. 101-112 [doi]
• XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architecturesXiaodong Wang, Jose F. Martinez. 113-125 [doi]
• Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memoriesMitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh. 126-136 [doi]
• Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applicationsYuhao Zhu, Matthew Halpern, Vijay Janapa Reddi. 137-149 [doi]
• Domain knowledge based energy management in handheldsNachiappan Chidambaram Nachiappan, Praveen Yedlapalli, Niranjan Soundararajan, Anand Sivasubramaniam, Mahmut T. Kandemir, Ravishankar Iyer, Chita R. Das. 150-160 [doi]
• GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architecturesJingwen Leng, Yazhou Zu, Vijay Janapa Reddi. 161-173 [doi]
• Mascar: Speeding up GPU warps by reducing memory pitstopsAnkit Sethia, Davoud Anoushe Jamshidi, Scott A. Mahlke. 174-185 [doi]
• Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchiesAlberto Ros, Mahdad Davari, Stefanos Kaxiras. 186-197 [doi]
• Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalabilityLucia G. Menezo, Valentin Puente, José-Ángel Gregorio. 198-209 [doi]
• Prediction-based superpage-friendly TLB designsMisel-Myrto Papadopoulou, Xin Tong, André Seznec, Andreas Moshovos. 210-222 [doi]
• Supporting superpages in non-contiguous physical memoryYu Du, Miao Zhou, Bruce R. Childers, Daniel Mossé, Rami G. Melhem. 223-234 [doi]
• Paying to save: Reducing cost of colocation data center via rewardsMohammad A. Islam, A. Hasan Mahmud, Shaolei Ren, Xiaorui Wang. 235-245 [doi]
• Octopus-Man: QoS-driven task management for heterogeneous multicores in warehouse-scale computersVinicius Petrucci, Michael A. Laurenzano, John Doherty, Yunqi Zhang, Daniel Mossé, Jason Mars, Lingjia Tang. 246-258 [doi]
• Understanding the virtualization "Tax" of scale-out pass-through GPUs in GaaS clouds: An empirical studyMing Liu, Tao Li, Neo Jia, Andy Currid, Vladimir Troy. 259-270 [doi]
• Adrenaline: Pinpointing and reining in tail queries with quick voltage boostingChang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, David Meisner, Thomas F. Wenisch, Jason Mars, Lingjia Tang, Ronald G. Dreslinski. 271-282 [doi]
• NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modulesAmin Farmahini Farahani, Jung Ho Ahn, Katherine Morrow, Nam Sung Kim. 283-295 [doi]
• Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systemsHao Wang, Chang-Jae Park, Gyungsu Byun, Jung Ho Ahn, Nam Sung Kim. 296-308 [doi]
• Reducing read latency of phase change memory via early read and Turbo ReadPrashant J. Nair, Chia-Chen Chou, Bipin Rajendran, Moinuddin K. Qureshi. 309-319 [doi]
• CAFO: Cost aware flip optimization for asymmetric memoriesRakan Maddah, Seyed Mohammad Seyedzadeh, Rami G. Melhem. 320-330 [doi]
• Understanding GPU errors on large-scale HPC systems and the implications for system design and operationDevesh Tiwari, Saurabh Gupta, James H. Rogers, Don Maxwell, Paolo Rech, Sudharshan S. Vazhkudai, Daniel A. G. de Oliveira, Dave Londo, Nathan DeBardeleben, Philippe Olivier Alexandre Navaux, Luigi Carro, Arthur S. Bland. 331-342 [doi]
• High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive cachesAamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer. 343-353 [doi]
• Unlocking bandwidth for GPUs in CC-NUMA systemsNeha Agarwal, David W. Nellans, Mike O'Connor, Stephen W. Keckler, Thomas F. Wenisch. 354-365 [doi]
• Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systemsManish Arora, Srilatha Manne, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen. 366-377 [doi]
• Power punch: Towards non-blocking power-gating of NoC routersLizhong Chen, Di Zhu, Massoud Pedram, Timothy Mark Pinkston. 378-389 [doi]
• Augmenting low-latency HPC network with free-space optical linksIkki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova. 390-401 [doi]
• SCOC: High-radix switches made of bufferless clos networksNikolaos Chrysos, Cyriel Minkenberg, Mark Rudquist, Claude Basso, Brian Vanderpool. 402-414 [doi]
• Overcoming far-end congestion in large-scale networksJongmin Won, Gwangsun Kim, John Kim, Ted Jiang, Mike Parker, Steve Scott. 415-427 [doi]
• iPatch: Intelligent fault patching to improve energy efficiencyDavid J. Palframan, Nam Sung Kim, Mikko H. Lipasti. 428-438 [doi]
• Balancing reliability, cost, and performance tradeoffs with FreeFaultDong-Wan Kim, Mattan Erez. 439-450 [doi]
• FTXen: Making hypervisor resilient to hardware faults on relaxed coresXinxin Jin, Soyeon Park, Tianwei Sheng, Rishan Chen, Zhiyong Shan, Yuanyuan Zhou. 451-462 [doi]
• Correction prediction: Reducing error correction latency for on-chip memoriesHenry Duwe, Xun Jian, Rakesh Kumar 0002. 463-475 [doi]
• Overcoming the challenges of crossbar resistive memory architecturesCong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie 0001. 476-488 [doi]
• Adaptive-latency DRAM: Optimizing DRAM timing for the common-caseDonghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu. 489-501 [doi]
• CiDRA: A cache-inspired DRAM resilience architectureYoung Hoon Son, Sukhan Lee, O. Seongil, Sanghyuk Kwon, Nam Sung Kim, Jung Ho Ahn. 502-513 [doi]
• Tag tablesSean Franey, Mikko H. Lipasti. 514-525 [doi]
• Architecture exploration for ambient energy harvesting nonvolatile processorsKaisheng Ma, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yongpan Liu, Jack Sampson, Yuan Xie 0001, Vijaykrishnan Narayanan. 526-537 [doi]
• Scaling distributed cache hierarchies through computation and data co-schedulingNathan Beckmann, Po-An Tsai, Daniel Sanchez. 538-550 [doi]
• Data retention in MLC NAND flash memory: Characterization, optimization, and recoveryYu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu. 551-563 [doi]
• GPGPU performance and power estimation using machine learningGene Y. Wu, Joseph L. Greathouse, Alexander Lyashevsky, Nuwan Jayasena, Derek Chiou. 564-576 [doi]
• Quantifying sources of error in McPAT and potential impacts on architectural studiesSam Likun Xi, Hans M. Jacobson, Pradip Bose, Gu-Yeon Wei, David M. Brooks. 577-589 [doi]
• Studying the impact of multicore processor scaling on directory techniques via reuse distance analysisMinshu Zhao, Donald Yeung. 590-602 [doi]
• SNNAP: Approximate computing on programmable SoCs via neural accelerationThierry Moreau, Mark Wyse, Jacob Nelson, Adrian Sampson, Hadi Esmaeilzadeh, Luis Ceze, Mark Oskin. 603-614 [doi]
• BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computingBeayna Grigorian, Nazanin Farahpour, Glenn Reinman. 615-626 [doi]
• Scalable communication architecture for network-attached acceleratorsSarah Neuwirth, Dirk Frey, Mondrian Nuessle, Ulrich Brüning. 627-638 [doi]
• Understanding contention-based channels and using them for defenseCasen Hunger, Mikhail Kazdagli, Ankit Singh Rawat, Alexandros G. Dimakis, Sriram Vishwanath, Mohit Tiwari. 639-650 [doi]
• Malware-aware processors: A framework for efficient online malware detectionMeltem Ozsoy, Caleb Donovick, Iakov Gorelik, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev. 651-661 [doi]
• Run-time monitoring with adjustable overhead using dataflow-guided filteringDaniel Lo, Tao Chen, Mohamed Ismail, G. Edward Suh. 662-674 [doi]