Table of Contents

• Amdahl's Law in the Datacenter Era: A Market for Fair Processor AllocationSeyed Majid Zahedi, Qiuyun Llull, Benjamin C. Lee. 1-14 [doi]
• iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-CoresYuan Yao, Zhonghai Lu. 15-26 [doi]
• Enabling Efficient Network Service Function Chain Deployment on Heterogeneous Server PlatformYang Hu, Tao Li. 27-39 [doi]
• Reducing Data Transfer Energy by Exploiting Similarity within a Data TransactionDonghyuk Lee, Mike O'Connor, Niladrish Chatterjee. 40-51 [doi]
• Making Memristive Neural Network Accelerators ReliableBen Feinberg, Shibo Wang, Engin Ipek. 52-65 [doi]
• Towards Efficient Microarchitectural Design for Accelerating Unsupervised GAN-Based Deep LearningMingcong Song, Jiaqi Zhang, Huixiang Chen, Tao Li. 66-77 [doi]
• Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural NetworksMinsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Stephen W. Keckler. 78-91 [doi]
• In-Situ AI: Towards Autonomous and Incremental Deep Learning for IoT SystemsMingcong Song, Kan Zhong, Jiaqi Zhang, Yang Hu, Duo Liu, Weigong Zhang, Jing Wang, Tao Li. 92-103 [doi]
• KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity MulticoresNosayba El-Sayed, Anurag Mukkara, Po-An Tsai, Harshad Kasture, Xiaosong Ma, Daniel Sánchez 0003. 104-117 [doi]
• SIPT: Speculatively Indexed, Physically Tagged CachesTianhao Zheng, Haishan Zhu, Mattan Erez. 118-130 [doi]
• Domino Temporal Data PrefetcherMohammad Bakhshalipour, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad. 131-142 [doi]
• ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and FairnessDmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström. 143-155 [doi]
• RCoal: Mitigating GPU Timing Attack via Subwarp-Based Randomized Coalescing TechniquesGurunath Kadam, Danfeng Zhang, Adwait Jog. 156-167 [doi]
• Are Coherence Protocol States Vulnerable to Information Leakage?Fan Yao, Milos Doroslovacki, Guru Venkataramani. 168-179 [doi]
• Record-Replay Architecture as a General Security FrameworkYasser Shalabi, Mengjia Yan, Nima Honarmand, Ruby B. Lee, Josep Torrellas. 180-193 [doi]
• The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM DevicesJeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu. 194-207 [doi]
• Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline StallsHongwen Dai, Zhen Lin, Chao Li 0004, Chen Zhao, Fei Wang, Nanning Zheng, Huiyang Zhou. 208-220 [doi]
• LATTE-CC: Latency Tolerance Aware Adaptive Cache Compression Management for Energy Efficient GPUsAkhil Arunkumar, Shin-Ying Lee, Vignesh Soundararajan, Carole-Jean Wu. 221-234 [doi]
• High-Performance GPU Transactional Memory via Eager Conflict DetectionXiaowei Ren, Mieszko Lis. 235-246 [doi]
• Efficient and Fair Multi-programming in GPUs via Effective Bandwidth ManagementHaonan Wang, Fan Luo, Mohamed Ibrahim, Onur Kayiran, Adwait Jog. 247-258 [doi]
• A Novel Register Renaming Technique for Out-of-Order ProcessorsHamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio González 0001. 259-270 [doi]
• Wait of a Decade: Did SPEC CPU 2017 Broaden the Performance Horizon?Reena Panda, Shuang Song, Joseph Dean, Lizy K. John. 271-282 [doi]
• Architectural Support for Task Dependence Management with Flexible Software SchedulingEmilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo 0001, José Luis Bosque, Ramón Beivide, Mateo Valero. 283-295 [doi]
• GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at RuntimeMagnus Jahre, Lieven Eeckhout. 296-309 [doi]
• Crash Consistency in Encrypted Non-volatile Main Memory SystemsSihang Liu, Aasheesh Kolli, Jinglei Ren, Samira Manabi Khan. 310-323 [doi]
• Adaptive Memory Fusion: Towards Transparent, Agile Integration of Persistent MemoryDongliang Xue, Chao Li, Linpeng Huang, Chentao Wu, Tianyou Li. 324-335 [doi]
• Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory SystemsMatheus Ogleari, Ethan L. Miller, Jishen Zhao. 336-349 [doi]
• Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCMSeyed Mohammad Seyedzadeh, Alex K. Jones, Rami G. Melhem. 350-361 [doi]
• Perception-Oriented 3D Rendering Approximation for Modern Graphics ProcessorsChenhao Xie, Xin Fu, Shuaiwen Song. 362-374 [doi]
• Warp Scheduling for Fine-Grained SynchronizationAhmed ElTantawy, Tor M. Aamodt. 375-388 [doi]
• WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUsKeunsoo Kim, Won Woo Ro. 389-402 [doi]
• G-TSC: Timestamp Based Coherence for GPUsAbdulaziz Tabbakh, Xuehai Qian, Murali Annavaram. 403-415 [doi]
• D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted MemoryRujia Wang, Youtao Zhang, Jun Yang 0002. 416-427 [doi]
• Secure DIMM: Moving ORAM Primitives Closer to MemoryAli Shafiee, Rajeev Balasubramonian, Mohit Tiwari, Feifei Li 0001. 428-440 [doi]
• Comprehensive VM Protection Against Untrusted Hypervisor Through Retrofitted AMD Memory EncryptionYuming Wu, Yutao Liu, Ruifeng Liu, Haibo Chen, Binyu Zang, Haibing Guan. 441-453 [doi]
• SYNERGY: Rethinking Secure-Memory Design for Error-Correcting MemoriesGururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi. 454-465 [doi]
• A Case for Packageless ProcessorsSaptadeep Pal, Daniel Petrisko, Adeel A. Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar 0002. 466-479 [doi]
• Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine LearningScott Van Winkle, Avinash Karanth Kodi, Razvan C. Bunescu, Ahmed Louri. 480-491 [doi]
• Routerless Network-on-ChipFawaz Alazemi, Arash AziziMazreah, Bella Bose, Lizhong Chen. 492-503 [doi]
• HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature AwarenessYixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu. 504-517 [doi]
• RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory DatabasesPeng Wang, Shuo Li, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai Li, Jason Cong, Nong Xiao, Tao Zhang. 518-530 [doi]
• GraphR: Accelerating Graph Processing Using ReRAMLinghao Song, Youwei Zhuo, Xuehai Qian, Hai Helen Li, Yiran Chen. 531-543 [doi]
• GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data PartitionMingxing Zhang, Youwei Zhuo, Chao Wang, Mingyu Gao, Yongwei Wu, Kang Chen, Christos Kozyrakis, Xuehai Qian. 544-557 [doi]
• PM3: Power Modeling and Power Management for Processing-in-MemoryChao Zhang, Tong Meng, Guangyu Sun. 558-570 [doi]
• Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup TagAlex Gendler, Arkady Bramnik, Ariel Szapiro, Yiannakis Sazeides. 571-582 [doi]
• Reliability-Aware Data Placement for Heterogeneous Memory ArchitectureManish Gupta, Vilas Sridharan, David Roberts, Andreas Prodromou, Ashish Venkat, Dean M. Tullsen, Rajesh K. Gupta 0001. 583-595 [doi]
• SmarCo: An Efficient Many-Core Processor for High-Throughput Applications in DatacentersDongrui Fan, Wenming Li, Xiaochun Ye, Da Wang, Hao Zhang 0009, Zhimin Tang, Ninghui Sun. 596-607 [doi]
• Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language LevelAnthony Gutierrez, Bradford M. Beckmann, Alexandru Dutu, Joseph Gross, Michael LeBeane, John Kalamatianos, Onur Kayiran, Matthew Poremba, Brandon Potter, Sooraj Puthoor, Matthew D. Sinclair, Mark Wyse, Jieming Yin, XianWei Zhang, Akshay Jain, Timothy Rogers. 608-619 [doi]
• Applied Machine Learning at Facebook: A Datacenter Infrastructure PerspectiveKim M. Hazelwood, Sarah Bird, David M. Brooks, Soumith Chintala, Utku Diril, Dmytro Dzhulgakov, Mohamed Fawzy, Bill Jia, Yangqing Jia, Aditya Kalro, James Law, Kevin Lee, Jason Lu, Pieter Noordhuis, Misha Smelyanskiy, Liang Xiong, Xiaodong Wang. 620-629 [doi]
• Amdahl's Law in Big Data Analytics: Alive and Kicking in TPCx-BB (BigBench)Daniel Richins, Tahrina Ahmed, Russell M. Clapp, Vijay Janapa Reddi. 630-642 [doi]
• Memory Hierarchy for Web SearchGrant Ayers, Jung Ho Ahn, Christos Kozyrakis, Parthasarathy Ranganathan. 643-656 [doi]
• Characterizing Resource Sensitivity of Database WorkloadsRathijit Sen, Karthik Ramachandra 0002. 657-669 [doi]
• ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System ParallelismSangkug Lym, Heonjae Ha, Yongkee Kwon, Chun-Kai Chang, Jungrae Kim, Mattan Erez. 670-682 [doi]
• DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High ReliabilitySeong-Lyong Gong, Jungrae Kim, Sangkug Lym, Michael Sullivan, Howard David, Mattan Erez. 683-695 [doi]
• Memory System Design for Ultra Low Power, Computationally Error Resilient Processor MicroarchitecturesSriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank. 696-709 [doi]
• NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for AcceleratorsNaveen Vedula, Arrvindh Shriraman, Snehasish Kumar, William N. Sumner. 710-723 [doi]
• OuterSPACE: An Outer Product Based Sparse Matrix Multiplication AcceleratorSubhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David Blaauw, Trevor N. Mudge, Ronald G. Dreslinski. 724-736 [doi]
• Searching for Potential gRNA Off-Target Sites for CRISPR/Cas9 Using Automata Processing Across Different PlatformsChunkun Bo, Vinh Dang, Elaheh Sadredini, Kevin Skadron. 737-748 [doi]
• Characterizing and Mitigating Output Reporting Bottlenecks in Spatial Automata Processing ArchitecturesJack Wadden, Kevin Angstadt, Kevin Skadron. 749-761 [doi]
• Power and Energy Characterization of an Open Source 25-Core Manycore ProcessorMichael McKeown, Alexey Lavrov, Mohammad Shahrad, Paul J. Jackson, Yaosheng Fu, Jonathan Balkind, Tri M. Nguyen, Katie Lim, Yanqi Zhou, David Wentzlaff. 762-775 [doi]
• A Spot Capacity Market to Increase Power Infrastructure Utilization in Multi-tenant Data CentersMohammad A. Islam, Xiaoqi Ren, Shaolei Ren, Adam Wierman. 776-788 [doi]
• GPGPU Power Modeling for Multi-domain Voltage-Frequency ScalingJoão Guerreiro, Aleksandar Ilic, Nuno Roma, Pedro Tomás. 789-800 [doi]