Abstract is missing.
- Evaluating energy efficiency of floating point matrix multiplication on FPGAsKiran Kumar Matam, Ming Hsieh. 1-6 [doi]
- A mechanism to improve the performance of hybrid MPI-OpenMP applications in gridShikha Mehrotra, K. V. Shamjith, Prachi Pandey, B. Asvija, R. Sridharan. 1-8 [doi]
- PAKCK: Performance and power analysis of key computational kernels on CPUs and GPUsJulia S. Mullen, Michael M. Wolf, Anna Klein. 1-6 [doi]
- Accelerating a novel particle-based fluid simulation on the GPUZhilu Chen, James Kingsley, Xinming Huang, Erkan Tüzel. 1-6 [doi]
- Block Processor: A resource-distributed architectureZe-ke Wang, Feng Yu, Xue Liu. 1-6 [doi]
- An improved eigensolver for quantum-dot cellular automata simulationsA. Taylor Baldwin, Jeffrey Will, Douglas Tougaw. 1-6 [doi]
- SIMD acceleration of modular arithmetic on contemporary embedded platformsKrishna Chaitanya Pabbuleti, Deepak Hanamant Mane, Avinash Desai, Curt Albert, Patrick Schaumont. 1-6 [doi]
- Standards for graph algorithm primitivesTim Mattson, David A. Bader, Jonathan W. Berry, Aydin Buluç, Jack Dongarra, Christos Faloutsos, John Feo, John R. Gilbert, Joseph Gonzalez, Bruce Hendrickson, Jeremy Kepner, Charles E. Leiserson, Andrew Lumsdaine, David A. Padua, Stephen Poole, Steve Reinhardt, Mike Stonebraker, Steve Wallach, Andrew Yoo. 1-2 [doi]
- Big snapshot stitching with scarce overlapAlexandros-Stavros Iliopoulos, Jun Hu, Nikos Pitsianis, Xiaobai Sun, Michael Gehm, David Brady. 1-6 [doi]
- Integrity verification for path Oblivious-RAMLing Ren, Christopher W. Fletcher, Xiangyao Yu, Marten van Dijk, Srinivas Devadas. 1-6 [doi]
- A nested dissection partitioning method for parallel sparse matrix-vector multiplicationErik G. Boman, Michael M. Wolf. 1-6 [doi]
- GPU accelerated blood flow computation using the Lattice Boltzmann MethodCosmin Nita, Lucian Mihai Itu, Constantin Suciu, Constantin Suciu. 1-6 [doi]
- Understanding query performance in AccumuloScott M. Sawyer, B. David O'Gwynn, An Tran, Tamara Yu. 1-6 [doi]
- Task scheduling for reconfigurable systems in dynamic fault-rate environmentsAdam Jacobs, Nicholas Wulf, Alan D. George. 1-6 [doi]
- A clustered manycore processor architecture for embedded and accelerated applicationsBenoît Dupont de Dinechin, Renaud Ayrignac, Pierre-Edouard Beaucamps, Patrice Couvert, Benoit Ganne, Pierre Guironnet de Massas, François Jacquet, Samuel Jones, Nicolas Morey Chaisemartin, Frédéric Riss, Thierry Strudel. 1-6 [doi]
- Biquad implementation of an IIR filter for IQ mismatch correction in an SoC RF receiverKaren Gettings, Andrew K. Bolstad, Michael N. Ericson, Xiao Wang. 1-5 [doi]
- Instruction set extensions for photonic synchronous coalesced accessesPaul Keltcher, David Whelihan, Jeffrey J. Hughes. 1-4 [doi]
- Vendor agnostic, high performance, double precision Floating Point division for FPGAsXin Fang, Miriam Leeser. 1-5 [doi]
- Robust graph traversal: Resiliency techniques for data intensive supercomputingSaurabh Hukerikar, Pedro C. Diniz, Robert F. Lucas. 1-6 [doi]
- Real-time traffic sign detection using SURF features on FPGAJin Zhao, Sichao Zhu, Xinming Huang. 1-6 [doi]
- Novel algebras for advanced analytics in JuliaViral B. Shah, Alan Edelman, Stefan Karpinski, Jeff Bezanson, Jeremy Kepner. 1-4 [doi]
- FPGA-based hyperspectral covariance coprocessor for size, weight, and power constrained platformsDavid A. Kusinsky, Miriam Leeser. 1-6 [doi]
- CrowdCL: Web-based volunteer computing with WebCLTommy MacWilliam, Cris Cecka. 1-6 [doi]
- D4M 2.0 schema: A general purpose high performance schema for the Accumulo databaseJeremy Kepner, Christian Anderson, William Arcand, David Bestor, Bill Bergeron, Chansup Byun, Matthew Hubbell, Peter Michaleas, Julie Mullen, David O'Gwynn, Andrew Prout, Albert Reuther, Antonio Rosa, Charles Yee. 1-6 [doi]
- Adaptive routing in hexagonal torus interconnection networksArash Shamaei, Bella Bose, Mary Flahive. 1-6 [doi]
- Dynamically configurable online statistical flow feature extractor on FPGADa Tong, Viktor K. Prasanna. 1-6 [doi]
- Software-Defined IDS for securing embedded mobile devicesRichard Skowyra, Sanaz Bahargam, Azer Bestavros. 1-7 [doi]
- Exploiting free silicon for energy-efficient computing directly in NAND flash-based solid-state storage systemsPeng Li, Kevin Gomez, David J. Lilja. 1-6 [doi]
- GPU-based space-time adaptive processing (STAP) for radarThomas M. Benson, Ryan K. Hersey, Edwin Culpepper. 1-6 [doi]
- Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardwareQiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry Pileggi, Franz Franchetti. 1-6 [doi]
- Miniature radar for mobile devicesPraveen Sharma, Raoul Ouedraogo, Bradley Perry, David Aubin, Todd Levy, Daniel Souza, Jonathan Kitchens, John Peabody. 1-8 [doi]
- High throughput energy efficient parallel FFT architecture on FPGAsRen Chen, Neungsoo Park, Viktor K. Prasanna. 1-6 [doi]
- GPU accelerated elevation map based registration of aerial imagesJoseph French, William F. Turri, Joseph Fernando, Eric J. Balster. 1-6 [doi]
- A novel fast modular multiplier architecture for 8, 192-bit RSA cryposystemWei Wang, Xinming Huang. 1-5 [doi]
- Re-Introduction of communication-avoiding FMM-accelerated FFTs with GPU accelerationHarper Langston, Muthu Manikandan Baskaran, Benoît Meister, Nicolas Vasilache, Richard Lethin. 1-6 [doi]
- LLSuperCloud: Sharing HPC systems for diverse rapid prototypingAlbert Reuther, Jeremy Kepner, William Arcand, David Bestor, Bill Bergeron, Chansup Byun, Matthew Hubbell, Peter Michaleas, Julie Mullen, Andrew Prout, Antonio Rosa. 1-6 [doi]
- 3D FFT for FPGAsBen Humphries, Martin C. Herbordt. 1-2 [doi]