Table of Contents

• Keynote talk I: Ending the Tyranny of Amdahl's Law Todd Austin. [doi]
• Design of high-performance, power-efficient optical NoCs using Silica-embedded silicon nanophotonicsElena Kakoulli, Vassos Soteriou, Charalambos Koutsides, Kyriacos Kalli. 1-8 [doi]
• A fast and energy efficient branch and bound algorithm for NoC task mappingJiashen Li, Yun Pan. 9-16 [doi]
• PID controlled thermal management in photonic network-on-chipDharanidhar Dang, Rabi N. Mahapatra, Eun Jung Kim. 17-23 [doi]
• Power-aware multi-voltage custom memory models for enhancing RTL and low power verificationVijay Kiran Kalyanam, Martin Saint-Laurent, Jacob A. Abraham. 24-31 [doi]
• Clustering-based revision debug in regression verificationDjordje Maksimovic, Andreas G. Veneris, Zissis Poulos. 32-37 [doi]
• SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationshipsPrateek Puri, Michael S. Hsiao. 38-45 [doi]
• Emulation-based selection and assessment of assertion checkers for post-silicon validationPouya Taatizadeh, Nicola Nicolici. 46-53 [doi]
• Exploring multiple sleep modes in on/off based energy efficient HPC networksKarthikeyan P. Saravanan, Paul M. Carpenter, Alex Ramírez. 54-61 [doi]
• Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCsMohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun. 62-69 [doi]
• Improving the interface performance of synthesized structural FAME simulators through schedulingDavid A. Penry. 70-77 [doi]
• Using M/G/l queueing models with vacations to analyze virtualized logic computationsMichael J. Hall, Roger D. Chamberlain. 78-85 [doi]
• An automated design flow for approximate circuits based on reduced precision redundancyDaniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino. 86-93 [doi]
• Logic simplification by minterm complement for error tolerant applicationHideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue. 94-100 [doi]
• Fault-tolerant in-memory crossbar computing using quantified constraint solvingAlvaro Velasquez, Sumit Kumar Jha. 101-108 [doi]
• Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latencyAli Ahari, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori. 109-116 [doi]
• Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnectsArseniy Vitkovskiy, Vassos Soteriou, Paul V. Gratz. 117-124 [doi]
• DLB: Dynamic lane borrowing for improving bandwidth and performance in Hybrid Memory CubeXianWei Zhang, Youtao Zhang, Jun Yang. 125-132 [doi]
• Memory design for selective error protectionYanan Cao, Long Chen, Zhao Zhang. 133-140 [doi]
• POS: A Popularity-based Online Scaling scheme for RAID-structured storage systemsSi Wu, Yinlong Xu, Yongkun Li, Yunfeng Zhu. 141-148 [doi]
• Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM cachesEishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura. 149-156 [doi]
• Exploit common source-line to construct energy efficient domain wall memory based cachesXianWei Zhang, Lei Zhao, Youtao Zhang, Jun Yang. 157-163 [doi]
• SCP: Synergistic cache compression and prefetchingBhargavraj Patel, Nikos Hardavellas, Gokhan Memik. 164-171 [doi]
• Application behavior aware re-reference interval prediction for shared LLCParth Lathigara, Shankar Balachandran, Virendra Singh. 172-179 [doi]
• InvArch: A hardware eficient architecture for Matrix InversionUmer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar. 180-187 [doi]
• Applied statistical inference for system design and managementBenjamin C. Lee. 188-191 [doi]
• Exploiting GPU architectures for dynamic invariant miningNicola Bombieri, Federico Busato, Alessandro Danese, Luca Piccolboni, Graziano Pravadelli. 192-195 [doi]
• ItHELPS: Iterative high-accuracy error localization in post-siliconValeria Bertacco, Wade Bonkowski. 196-199 [doi]
• An orchestrated approach to efficiently manage resources in heterogeneous system architecturesCristiana Bolchini, Gianluca C. Durelli, Antonio Miele, Gabriele Pallotta, Marco D. Santambrogio. 200-207 [doi]
• Energy-efficient execution of data-parallel applications on heterogeneous mobile platformsAlok Prakash, Siqi Wang, Alexandru Eugen Irimiea, Tulika Mitra. 208-215 [doi]
• Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applicationsJude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran. 216-223 [doi]
• Cyber-physical integration in programmable microfluidic biochipsTsung-Yi Ho, William Grover, Shiyan Hu, Krishnendu Chakrabarty. 224-227 [doi]
• SOP based logic synthesis for memristive IMPLY stateful logicFelipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas. 228-235 [doi]
• CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reductionChen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen. 236-243 [doi]
• A pre-search assisted ILP approach to analog integrated circuit routingChia-Yu Wu, Helmut Graeb, Jiang Hu. 244-250 [doi]
• Trace-based automated logical debugging for high-level synthesis generated circuitsPietro Fezzardi, Michele Castellana, Fabrizio Ferrandi. 251-258 [doi]
• Physical synthesis of DNA circuits with spatially localized gatesJinwook Jung, Daijoon Hyun, Youngsoo Shin. 259-265 [doi]
• Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systemsVinayaka Jyothi, Sateesh Addepalli, Ramesh Karri. 266-272 [doi]
• 3D Integration: New opportunities in defense against cache-timing side-channel attacksChongxi Bao, Ankur Srivastava. 273-280 [doi]
• Side-channel power analysis of a GPU AES implementationChao Luo, Yunsi Fei, Pei Luo, Saoni Mukherjee, David R. Kaeli. 281-288 [doi]
• Performance optimization for on-chip sensors to detect recycled ICsBicky Shakya, Ujjwal Guin, Mark Mohammad Tehranipoor, Domenic Forte. 289-295 [doi]
• From theory to practice of private circuit: A cautionary noteDebapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay. 296-303 [doi]
• Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applicationsHamid Reza Ghasemi, Ulya R. Karpuzcu, Nam Sung Kim. 304-310 [doi]
• Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processorsMahanama Wickramasinghe, Hui Guo. 311-318 [doi]
• Dynamic core scaling: Trading off performance and energy beyond DVFSWei Zhang, Hang Zhang, John Lach. 319-326 [doi]
• Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable coreSudarshan Srinivasan, Israel Koren, Sandip Kundu. 327-334 [doi]
• Fast boolean logic mapped on memristor crossbarLei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Koen Bertels, Said Hamdioui. 335-342 [doi]
• Reliable and high performance STT-MRAM architectures based on controllable-polarity devicesKaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael T. Niemier, Xiaobo Sharon Hu. 343-350 [doi]
• Increasing reconfigurability with memristive interconnectsJohn Demme, Bipin Rajendran, Steven M. Nowick, Simha Sethumadhavan. 351-358 [doi]
• Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settingsManqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti. 359-366 [doi]
• A thermal adaptive scheme for reliable write operation on RRAM based architecturesFernando Garcia-Redondo, Marisa López-Vallejo, Pablo Ituero. 367-374 [doi]
• Power management of pulsed-index communication protocolsShahzad Muzaffar, Ibrahim Abe M. Elfadel. 375-378 [doi]
• Big data on low power cores: Are low power embedded processors a good fit for the big data workloads?Maria Malik, Houman Homayoun. 379-382 [doi]
• Energy-optimal voltage model supporting a wide range of nodal switching rates for early design-space explorationDoyun Kim, Jiangyi Li, Mingoo Seok. 383-386 [doi]
• On the conditions of guaranteed k-fault tolerant systems supporting on-the-fly repairsSoumya Banerjee, Wenjing Rao. 387-390 [doi]
• Exploring the viability of stochastic computingJoao Marcos de Aguiar, Sunil P. Khatri. 391-394 [doi]
• A new encoding mechanism for low power inter-chip serial communication in asynchronous circuitsTomohiro Yoneda, Masashi Imai. 395-398 [doi]
• Energy-efficient data movement with sparse transition encodingYanwei Song, Mahdi Nazm Bojnordi, Engin Ipek. 399-402 [doi]
• A low power buffer-aided vector register file for LTE baseband signal processingZhiguo Liu, Ziyuan Zhu, Jinglin Shi, Jinbao Liu, Shiqiang Li. 403-406 [doi]
• An aging-aware battery charge scheme for mobile devices exploiting plug-in time patternsAlberto Bocca, Alessandro Sassone, Alberto Macii, Enrico Macii, Massimo Poncino. 407-410 [doi]
• Analytic processor model for fast design-space explorationRik Jongerius, Giovanni Mariani, Andreea Anghel, Gero Dittmann, Erik Vermij, Henk Corporaal. 411-414 [doi]
• A pair selection algorithm for robust RO-PUF against environmental variations and agingMd. Tauhidur Rahman, Domenic Forte, Fahim Rahman, Mark Tehranipoor. 415-418 [doi]
• Chameleon: Adaptive energy-efficient heterogeneous network-on-chipJi Wu, Dezun Dong, Xiangke Liao, Li Wang. 419-422 [doi]
• Combative cache efficacy techniques: Cache replacement in the context of independent prefetching in last level cacheCesar Gomes, Mark Hempstead. 423-426 [doi]
• Shift-aware racetrack memoryEhsan Atoofian, Ahsan Saghir. 427-430 [doi]
• ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuitsSatish Grandhi, David McCarthy, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana. 431-434 [doi]
• Data-driven logic synthesizer for acceleration of Forward propagation in artificial neural networksKhaled Z. Mahmoud, William E. Smith, Mark Fishkin, Timothy N. Miller. 435-438 [doi]
• Fixed-function hardware sorting accelerators for near data MapReduce executionSeth H. Pugsley, Arjun Deb, Rajeev Balasubramonian, Feifei Li. 439-442 [doi]
• Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuitsYufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula. 443-446 [doi]
• Exploiting request characteristics and internal parallelism to improve SSD performanceBo Mao, Suzhen Wu. 447-450 [doi]
• FDRAM: DRAM architecture flexible in successive row and column accessesJeongjae Yu, Wooyoung Jang. 451-454 [doi]
• Runtime multi-optimizations for energy efficient on-chip interconnections1Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura. 455-458 [doi]
• A hardware-based multi-objective thread mapper for tiled manycore architecturesRavi Kumar Pujari, Thomas Wild, Andreas Herkersdorf. 459-462 [doi]
• Automatic identification of assertions and invariants with small numbers of test vectorsMasahiro Fujita. 463-466 [doi]
• A novel 3D graphics DRAM architecture for high-performance and low-energy memory accessesIshan G. Thakkar, Sudeep Pasricha. 467-470 [doi]
• M-MAP: Multi-factor memory authentication for secure embedded processorsSyed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk. 471-474 [doi]
• Acceleration of microwave imaging algorithms for breast cancer detection via High-Level SynthesisDaniele Jahier Pagliari, Mario R. Casu, Luca P. Carloni. 475-478 [doi]
• Power and performance characterization, analysis and tuning for energy-efficient edge detection on atom and ARM based platformsPaul Otto, Maria Malik, Nima Akhlaghi, Rebel Sequeira, Houman Homayoun, Siddhartha Sikdar. 479-482 [doi]
• Security implications of cyberphysical digital microfluidic biochipsSk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri. 483-486 [doi]
• Hardware support for production run diagnosis of performance bugsAbdullah Muzahid. 487-490 [doi]
• A methodology for power characterization of associative memoriesDawei Li, Siddhartha Joshi, Seda Ogrenci Memik, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, Nhan Tran. 491-498 [doi]
• Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technologyPasquale Corsonello, Stefania Perri, Fabio Frustaci. 499-504 [doi]
• A wirelessly powered system with charge recovery logicLeo Filippini, Emre Salman, Baris Taskin. 505-510 [doi]
• Reactive clocks with variability-tracking jitterJordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar. 511-518 [doi]
• Methods for analysing and improving the fault resilience of delay-insensitive codesJakob Lechner, Andreas Steininger, Florian Huemer. 519-526 [doi]
• Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regimeYuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander Shapiro, Engin Ipek, Eby G. Friedman. 527-534 [doi]
• VLSI implementation of high-throughput, low-energy, configurable MIMO detectorPierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet. 535-542 [doi]
• Exploring early and late ALUs for single-issue in-order pipelinesAlen Bardizbanyan, Per Larsson-Edefors. 543-548 [doi]
• Improving memristor memory with sneak current sharingManjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon. 549-556 [doi]
• Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systemsSudhanshu Shukla, Mainak Chaudhuri. 557-564 [doi]
• A multicore vacation scheme for thermal-aware packet processingChih-Hsun Chou, Laxmi N. Bhuyan. 565-572 [doi]
• Dark silicon aware runtime mapping for many-core systems: A patterning approachAnil Kanduri, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Axel Jantsch, Hannu Tenhunen. 573-580 [doi]
• Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mappingMohammad Khavari Tavana, Divya Pathak, Mohammad Hossein Hajkazemi, Maria Malik, Ioannis Savidis, Houman Homayoun. 581-588 [doi]
• Cache allocation for fixed-priority real-time scheduling on multi-core platformsGustavo A. Chaparro-Baquero, Soamar Homsi, Omara Vichot, Shaolei Ren, Gang Quan, Shangping Ren. 589-596 [doi]
• A novel TSV probing technique with adhesive test interposerLi Jiang, Xiangwei Huang, Hongfeng Xie, Qiang Xu, Chao Li, Xiaoyao Liang, Huiyun Li. 597-604 [doi]
• A methodology to generate evenly distributed input stimuli by clustering of variable domainM. P. Jomu George, Otmane Aït Mohamed. 605-612 [doi]
• A scan chain optimization method for diagnosisHuajun Chen, Zichu Qi, Lin Wang, Chao Xu. 613-620 [doi]
• A one-pass test-selection method for maximizing test coverageCheng Xue, R. D. (Shawn) Blanton. 621-628 [doi]
• Non-enumerative correlation-aware path selectionAhish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi. 629-634 [doi]
• RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memorySu Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran. 635-642 [doi]
• Power-agility metrics: Measuring dynamic characteristics of energy proportionalityRizwana Begum, Mark Hempstead. 643-650 [doi]
• VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypesSanthosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal. 651-658 [doi]
• TriState-SET: Proactive SET for improved performance of MLC phase change memoriesXianWei Zhang, Youtao Zhang, Jun Yang. 659-665 [doi]
• OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterizationJie Zhang, Gieseo Park, Mustafa Shihab, David Donofrio, John Shalf, Myoungsoo Jung. 666-673 [doi]
• GPU acceleration for PCA-based statistical static timing analysisYiren Shen, Jiang Hu. 674-679 [doi]
• Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysisVinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis. 680-687 [doi]
• Optimized local control strategy for voice-based interaction-tracking badges for social applicationsXiaowei Liu, Alex Doboli, Fan Ye. 688-695 [doi]
• FPGA-SPICE: A simulation-based power estimation framework for FPGAsXifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 696-703 [doi]
• Energy-efficient implementations of GF (p) and GF(2m) elliptic curve cryptographyAndrew D. Targhetta, Donald E. Owen, Francis L. Israel, Paul V. Gratz. 704-711 [doi]
• Hybrid scratchpad and cache memory management for energy-efficient parallel HEVC encodingChang Song, Lei Ju, Zhiping Jia. 712-719 [doi]
• Mobile ecosystem driven application-specific low-power control microarchitectureGaro Bournoutian, Alex Orailoglu. 720-727 [doi]
• Resilient mobile cognition: Algorithms, innovations, and architecturesR. Viguier, C. C. Lin, K. Swaminathan, A. Vega, Alper Buyuktosunoglu, S. Pankanti, P. Bose, H. Akbarpour, Filiz Bunyak, Kannappan Palaniappan, Guna Seetharaman. 728-731 [doi]
• A testing platform for on-drone computationWang Zhou, Dhruv Nair, Oki Gunawan, Theodore G. van Kessel, Hendrik F. Hamann. 732-735 [doi]
• Resilient, UAV-embedded real-time computingAugusto Vega, Chung-Ching Lin, Karthik Swaminathan, Alper Buyuktosunoglu, Sharathchandra Pankanti, Pradip Bose. 736-739 [doi]