Table of Contents

• HElix: Genome Similarity Detection in the Encrypted DomainRostin Shokri, Charles Gouert, Nektarios Georgios Tsoutsos. 1-8 [doi]
• Hammering the Diagnosis: Rowhammer-Induced Stealthy Trojan Attacks on ViT-Based Medical ImagingBanafsheh Saber Latibari, Najmeh Nazari, Hossein Sayadi, Houman Homayoun, Abhijit Mahalanobis. 1-8 [doi]
• RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-VWanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang 0001, Naifeng Jing, Qin Wang 0009. 1-8 [doi]
• Tips: Augment Memory Tagging to Defend Against Prefetcher Side ChannelsYubiao Huang, Peinan Li, Huan Qiao, Yunkai Bai, Shiwen Wang 0002, Dan Meng 0002, Rui Hou 0001. 1-8 [doi]
• FINEA: An Efficient Neural Network Accelerator Exploiting Factorized Input FeaturesYujin Kim, Chanhun Jeong, Yunho Oh, Myung Kuk Yoon, Gunjae Koo. 1-9 [doi]
• 2Hash: A Read-Optimized and Resize-Friendly Hashing Index for Persistent MemoryJinlei Hu, Bo Chen, Miaosong Zhang, Jing Hu, Jianxi Chen, Dan Feng 0001. 1-9 [doi]
• Targeted Fault Injection Attack on Semantic Segmentation ModelsJhon Ordoñez, Chengmo Yang. 9-16 [doi]
• Towards Low-Latency and Adaptive Ransomware Detection Using Contrastive LearningZhixin Pan, Ziyu Shu, Amberbir Alemayoh. 17-24 [doi]
• SecNPU: Securing LLM Inference on NPUXuanyao Peng, Yinghao Yang 0001, Shangjie Pan, Junjie Huang, Yujun Liang, Hang Lu, Fengwei Zhang, Xiaowei Li 0001. 25-32 [doi]
• DMP-BFP: Dynamic Mixed-Precision Block Floating-Point and Exponent-Guided Precision AdjustmentYu-Chih Tsai, Chia-Cheng Chang, Ren-Shuo Liu. 33-40 [doi]
• Hardware Efficient Multiplier Design Using an Optimal Mix of Approximate Booth EncodingsChandan Kumar N. S, Bhavana S, Ajitesh Kumar Singh, Madhav Rao. 41-48 [doi]
• PolyPE: An Efficient Multi-Precision Multi-Mode Floating-Point Processing Element for HPC and AIZhenzhen Jia, Hongbing Tan, Ling Yang 0008, Hui Guo 0004, Kun Zeng, Junsheng Chang, Yongwen Wang, Libo Huang. 49-56 [doi]
• CHQ-SC: Compact and High-Quality Stochastic Computing Framework Using Magnetic Tunnel JunctionYu Ma, Jianmin Zhang, Yan Sun, Siqing Fu. 57-60 [doi]
• RAM-Wafer: RL-Based Automatic Mapping Framework for Large-Scale AI Training on Wafer-Scale ComputingXu Dai, Dehao Kong, Xufeng He, Zijun Xu, Shaopeng Zhai, Yang Hu 0001, Shouyi Yin. 61-69 [doi]
• DHeLlam: General-Purpose, Automatic Micro-Batch Co-Execution for Distributed LLM TrainingHaiquan Wang, Chaoyi Ruan, Jia He, Jiaqi Ruan, Chengjie Tang, Xiaosong Ma, Cheng Li 0001. 70-78 [doi]
• A Co-Design Framework for Graph Processing on CPU-GPU Heterogeneous PlatformsYuan Zhang 0031, Huawei Cao, Yiming Sun, Ming Dun, Jie Zhang 0130, Xiaochun Ye. 79-86 [doi]
• Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous PlatformsTong Qiao, Ao Zhou, Yingjie Qi, Yiou Wang, Han Wan, Jianlei Yang 0001, Chunming Hu. 87-94 [doi]
• Enhancing Transformer Inference Efficiency on FPGA Through Fully Fusion and Integer-Only Quantization TechniquesZhenqi Li, Yuan Li, Mingche Lai, Puguang Liu, Qiang Wang, Yankang Zhao, Hanyuan Li, Xingyun Qi. 95-102 [doi]
• RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer AccelerationLei Zhao, Aishwarya Natarajan, Luca Buonanno, Archit Gajjar, Ron M. Roth, Sergey Serebryakov, John Moon, Omar Eldash, Jim Ignowski, Giacomo Pedretti. 103-110 [doi]
• PACE-Lite: Compact and Efficient Piecewise Polynomial Approximation for Transformer Nonlinearity AccelerationArpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi 0001, Francesco Conti 0001, Luca Benini. 111-118 [doi]
• QuFi: Adaptive Tiled Gustavson Output Reuse for Edge Sparse DNN AcceleratorsAdrián Navarro, José Cano 0001, José L. Abellán, Manuel E. Acacio. 119-126 [doi]
• HBM-Aware Number Theoretic Transform Accelerator for Zero-Knowledge ProofSangwon Shin, Ngoc-Son Pham, Lei Xu 0012, Weidong Shi, Taeweon Suh. 127-130 [doi]
• Repo: Proactive Swapping Exploiting Loop Patterns in Modern ApplicationsJiahui Zhang, Qiang Cao 0001, Yekang Zhan, Yuchen Hu, Jie Yao 0001. 131-138 [doi]
• RT-PMalloc: Optimizing Persistent Memory Allocation for Soft Real-Time SystemsYuquan Chi, Yinjin Fu, Nong Xiao. 139-146 [doi]
• A Scalable and Overflow-Tolerant Mechanism for Minimum Virtual Time TrackingGyusun Lee, Seungwoo Jin, Jiwon Woo, Jinkyu Jeong. 147-154 [doi]
• CAST: An Efficient Framework for Schedules Performance Prediction Based on Compact ASTsQingqiu Lan, Ao Ren, Zhenyu Wang, Wei Li, Hongbin Zhu, Yujuan Tan, Duo Liu, Kan Zhong, Chaoxia Qin. 155-158 [doi]
• STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D IntegrationVarun Darshana Parekh, Zachary Wyatt Hazenstab, Srivatsa Rangachar Srinivasa, Krishnendu Chakrabarty, Kai Ni 0004, Vijaykrishnan Narayanan. 159-166 [doi]
• OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark SuiteShan Shen, Xingyang Li, Zhuohua Liu, Junhao Ma, Yikai Wang, Yiheng Wu, Yuquan Sun, Wei W. Xing. 167-175 [doi]
• 3DPX - An Open-Source Methodology for 3D Physical Design ExplorationGeorge Goudroumanis, Maria Pantazi-Kypraiou, George Floros 0002, Athanasios Tziouvaras, Georgios I. Stamoulis, Alberto García Ortiz. 176-179 [doi]
• Declarative Synthesis and Multi-Objective Optimization of Stripboard Circuit Layouts Using Answer Set ProgrammingFang Li. 180-183 [doi]
• ALPHA: A Scalable Lock-Free Partitioned Hash Index for Persistent Memory on NUMA ArchitecturesQiyang Zheng, Hao Hu, Hao Huang, Yanqi Pan, Yifeng Zhang, Wen Xia, Xiangrui Meng, Xudong Li. 193-200 [doi]
• DDLM: Demand-Aware Dynamic Link Width Management for Energy-Efficient CXL MemoryTaejeong Kim, Junbum Park, Yongho Lee, Seokin Hong. 201-208 [doi]
• Computing-in-Memory Dataflow for Minimal Buffer TrafficChoongseok Song, Doo Seok Jeong. 209-216 [doi]
• PIMFY: Eliminating Remote Page Walks in MCM GPUsJunsung Kim, SungWoo Kim, Seunghyun Jin, Won Woo Ro. 217-220 [doi]
• PriME: PIM-Aware Efficient Compression for Memory-Bound Embedding Layers in sLLMsJunghyeok Lee, Jihoon Jang, Hyun Kim. 221-228 [doi]
• CMC: Compound Memory-Computing Architecture for Energy-Efficient CNN AcceleratorsMing Han, Jin Wu, Jian Dong 0010, Ye Wang, Gang Qu 0001. 229-236 [doi]
• Dissecting and Re-Architecting 3D NAND Flash PIM Arrays for Efficient Single-Batch Token Generation in LLMSYongjoo Jang, Sangwoo Hwang, Hojin Lee, Sangwoo Jung, Donghun Lee, Wonbo Shim, Jaeha Kung. 237-244 [doi]
• MamCIMFlow: An Integrated Co-Design of RRAM-Based CIM and Selective State-Space Streaming for Efficient Mamba Model AccelerationMingzi Li, Zhongrui Wang, Zhongwen Ye, Tao Pan, Han Wang. 245-248 [doi]
• PIM-SUM: Fast and Reliable In-Memory Summation for Recommendation SystemsFan Li, Ruizhi Zhu, Huize Li, Di Wu, Xin Xin. 249-252 [doi]
• Ghidorah: Fast LLM Inference on Edge with Speculative Decoding and Hetero-Core ParallelismJinhui Wei, Ye Huang, Yuhui Zhou, Jiazhi Jiang, Jiangsu Du. 253-260 [doi]
• DualSpar: A Dual-Granularity Memory Framework with Adaptive Sparsity for Efficient LLM InferenceYujuan Tan, Jiayi Guo, Zhuoxin Bai, Sanle Zhao, Yujiao Wang, Zongjie Wang, Ao Ren, Kan Zhong, Lin Huang, Jun Liu. 261-268 [doi]
• Throughput-Oriented LLM Inference via KV-Activation Hybrid Caching with A Single GPUSanghyeon Lee, Hongbeen Kim, Soojin Hwang, Guseul Heo, Minwoo Noh, Jaehyuk Huh 0001. 269-276 [doi]
• AuLoRA: Fine-Grained Loading and Computation Orchestration for Efficient LoRA LLM ServingXiao Shi, Jiangsu Du, Zhiguang Chen 0001, Yutong Lu. 277-284 [doi]
• Taming Sparse Giants: Deploying Mixture-of-Experts on 3D Heterogeneous Compute-in-Memory SystemsPragya Sharma, Ashish Reddy Bommana, Farshad Firouzi, Krishnendu Chakrabarty. 285-288 [doi]
• $\mu\text{STT}$: Microarchitecture Design for Speculative Taint TrackingBoru Chen, Rutvik Choudhary, Kaustubh Khulbe, Archie Lee, Adam Morrison 0001, Christopher W. Fletcher. 289-297 [doi]
• Hot-FV: A Semi-Formal Test Generation Framework for RTL Functional Coverage Using Warm Starting StatesZiyue Zheng, Zhiyuan Yan 0003, Xiangchen Meng, Guangyu Hu, Hongce Zhang, Yangdi Lyu. 298-305 [doi]
• ATPG-Based Weighted Scan Chain Control for Programmable Low-Power LBISTYumei Hu, Hairui Cai, Xiaohui Xue, Yaning Wang, Yu Huang, Zhipeng Lv, Zhouxing Su, Zezhong Wang, Xing Wang. 306-314 [doi]
• FitFuzz: Depth-Oriented Coverage-Guided Fuzzing via Fitness-Based Seed SchedulingVenkat Nitin Patnala, Sai Manoj Pudukotai Dinakarrao. 315-318 [doi]
• DASICS: Efficient In-Process Protection with Hardware-Assisted Dynamic CompartmentalizationYue Jin, Yibin Xu, Han Wang, Chengyuan Zhang, Tianyi Huang, Tianyue Lu, Mingyu Chen 0001. 319-322 [doi]
• Security Evaluation of Quantum Circuit Split Compilation Under an Oracle-Guided AttackHongyu Zhang, Yuntao Liu. 323-328 [doi]
• Forensics of Error Rates of Quantum HardwareRupshali Roy, Swaroop Ghosh. 329-334 [doi]
• QTIME: A Machine Learning Framework for Timing Side-Channel Analysis in Quantum Circuit SimulatorsBen Dong, Hui Feng, Qian Wang. 335-341 [doi]
• Recovering QSVT Polynomials from Side-Channel Information on Quantum ComputersKidus Tessma, Hrvoje Kukina, Jakub Szefer. 342-347 [doi]
• Concolic Testing for Quantum CompilersNavnil Choudhury, Ameya S. Bhave, Kanad Basu. 348-355 [doi]
• UQ-VarQA: Benchmarking and Characterizing NISQ Computers Through Uncertainty Quantification of Variational Quantum AlgorithmsPriyabrata Senapati, Shengye Zhu, Bo Peng, Bo Fang 0002, Qiang Guan. 356-363 [doi]
• NaviMap: Partial Order-Guided Neural Architecture via Deep Q-Networks for Efficient CGRA MappingMingyang Kou, Jun Zeng 0001, Xinyu Peng, Weiqing Ji, Hailong Yao 0002. 364-371 [doi]
• IasRT: Interference-Aware and SLO-Driven GPU Scheduling for Real-Time DNN InferenceHeming Zhong, Jinhui Wei, Yujia Fu, Dan Huang 0001, Yutong Lu. 372-379 [doi]
• AICAWS: Arithmetic Intensity Based Cache-Conscious Adaptive Warp SchedulerBo Yuan, Sheng Liu, Zekun Jiang, Jianfeng Cui, Yang Guo. 380-388 [doi]
• A Dynamic Virtual Memory Management System for LLMs on AI ChipsGaolin Wei, Zhaorui Zhang, Jiaqi Xu, Chen Jason Zhang, Xin Yao, Benben Liu. 389-392 [doi]
• CPA-Remap: Critical-Path-Based Physically Aware Remapping Framework for Timing OptimizationMingxiao He, Pengcheng Huang, Zhenyu Zhao, Peiyun Bian. 393-400 [doi]
• Threshold Voltage Tuning Technique for Leakage Power RecoveryJaejoon Yoon, Taewhan Kim. 401-408 [doi]
• Timing-Driven Global Placement with Entropy-Mobility Guided Pin-to-Pin WeightingYouzhi Zheng, Zhengjie Zhao, Linhao Lu, Xiaodong Zhu, Wenxin Yu 0001, Jingwei Lu. 409-415 [doi]
• Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization TechniquesYeongyeong Shin, Sehyeon Chung, Taewhan Kim 0001. 416-423 [doi]
• GAN-BiLSTM-HDC: A Hybrid Framework for Robust and Hardware-Efficient Malware DetectionEmilien Meyer, Abu Kaisar Mohammad Masum, Mehran Shoushtari Moghadam, Lida Kouhalvandi, Gourav Datta, Sercan Aygun, M. Hassan Najafi. 424-431 [doi]
• LM-Fix: Lightweight Bit-Flip Detection and Rapid Recovery Framework for Language ModelsAhmad Tahmasivand, Noureldin Zahran, Saba Al-Sayouri, Mohamed E. Fouda, Khaled N. Khasawneh. 432-440 [doi]
• FaRAccel: FPGA-Accelerated Defense Architecture for Efficient Bit-Flip Attack Resilience in Transformer ModelsNajmeh Nazari, Banafsheh Saber Latibari, Elahe Hosseini, Fatemeh Movafagh, Chongzhou Fang, Hosein Mohammadi Makrani, Kevin Immanuel Gubbi, Abhijit Mahalanobis, Setareh Rafatirad, Hossein Sayadi, Houman Homayoun. 441-449 [doi]
• Hybrid-Rewrite: A Rewriting Framework for Hybrid Deduplication and Delta CompressionQiao Li, Hong Jiang, Yucheng Zhang, Zichen Xu, Junyun Wu, Puchen Lu. 458-465 [doi]
• NatSep: Little-to-No Overhead Data Separation for Log-Structured Storage Using Native InformationJinLong Wang, Zhipeng Tan, Yang Xiao, Wenjie Qi, Shikai Tan, Ying Yuan. 466-473 [doi]
• The Logic of Fingerprint Upgrade in Deduplicated StorageCai Deng, Boju Chen, Philip Shilane, Xiangyu Zou, Wen Xia, Hao Hu. 474-481 [doi]
• Pixel-DNA: Increasing Robustness of Approximate DNA Storage for Images by Using Hierarchical DeduplicationAlex Sensintaffar, David Du 0001, Bingzhe Li. 482-490 [doi]
• TCFlash: In-Flash Bulk Bitwise Processing via Dynamic Sensing and TLC Encoding in 3D NANDHabib Ur Rahman, Tharini Suresh, Sudeep Pasricha, Biswajit Ray. 491-494 [doi]
• Minimizing Read Disturb via Localized Page Allocation for Modern NAND Flash-Based SSDsJoonseong Hwang, Minkyu Choi, Minjin Park, Jihun Yoon, Yoonho Jang, Seokin Hong. 495-498 [doi]
• Laser and Radiation Testing of Compiler-Based Protection for Multi-Bit UpsetsDavide Baroffio, Tomas Antonio Lopez, Federico Reghenzani, William Fornaciari. 499-506 [doi]
• Masked Gadgets for Integer-Floating-Point Conversion with Applications to FalconShuyi Chen, Jingdian Ming, Yuejun Liu, Yiwen Gao 0001, Yongbin Zhou. 507-514 [doi]
• WSSR: Weight Set Segmentation and Recovery for Fault Resilient TransformersNtsee Ndingwan, Chengmo Yang. 515-522 [doi]
• ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCsIshraq Tashdid, Dewan Saiham, Nafisa Anjum, Tasnuva Farheen, Sazadur Rahman. 523-527 [doi]
• Enhancing Key-Recovery Chosen-Ciphertext Side-Channel Attacks on NTRU Using LDPCDenis Nabokov, Xiaofei Tong, Qian Guo. 528-531 [doi]
• A Photonic Accelerator for Deep Learning TrainingYuan Li. 532-539 [doi]
• Flame: A Multiplier-Free LLM Accelerator with Dynamic Block Floating PointAo Lyu, Haishuang Fan, Guihai Yan. 549-557 [doi]
• Hermes: Accelerating Packet Processing in DPU with Neural NetworkRui Meng, Xinyu Chen 0001, Hanyue Lin, Jingya Wu, Wenyan Lu, Xiaowei Li 0001, Guihai Yan. 558-561 [doi]
• ASMA: An Anisotropy Scaling Memristor-Based Accelerator for LLM InferenceZijian Xiong, Xiangrui Yang, Yuhang Zhang, Yue Zhou, Jianguo Yang, Yaoyu Tao, Xiangshui Miao, Yuhui He. 562-565 [doi]
• RTLBench: A Multi-Dimensional Benchmark Suite for Evaluating LLM-Generated RTL CodeZhigang Fang 0002, Renzhi Chen, Yang Guo 0003, Huadong Dai, Lei Wang 0011. 566-573 [doi]
• SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code GenerationM. Zafir Sadik Khan, Nowfel Mashnoor, Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali. 574-581 [doi]
• Llm4mcu-Onto: Leveraging Llms for Automated Ontology Generation From Microcontroller Reference ManualAsmita 0001, Grisha Bandodkar, Sujan Ghimire, Shaurya Srivastav, Soheil Salehi, Houman Homayoun. 582-589 [doi]
• LLM-Driven Code Generation for Neural Networks on FPGAs: Bridging Python and HLSRupesh Raj Karn, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu. 590-593 [doi]
• TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity WorkloadsNavaneeth Kunhi Purayil, Diyou Shen, Matteo Perotti, Luca Benini. 594-601 [doi]
• TeraNOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory ClustersYichao Zhang 0003, Zexin Fu, Tim Fischer 0001, Yinrong Li, Marco Bertuletti, Luca Benini. 610-617 [doi]
• Thena: Torus Fully Homomorphic Encryption on Energy-Efficient Heterogeneous ArchitectureYanze Wu, Md Tanvir Arafin. 618-625 [doi]
• SSM-RDU: A Reconfigurable Dataflow Unit for Long-Sequence State-Space ModelsSho Ko, Kunle Olukotun. 626-629 [doi]
• Optimization of Wire Pipelining and Channel Parallelism for 2D-Mesh NoC Physical DesignPei-Huan Tsai, Maico Cassel dos Santos, Joseph Zuckerman, Kuan-Lin Chiu, Luca P. Carloni. 630-637 [doi]
• Agile Design Flow for Cryptographic Hardware AcceleratorsLiming Deng, Guowei Zhu, Wei Cao 0002, Xitian Fan, Xuegong Zhou. 638-645 [doi]
• Decomposition Attack on Structural Logic Locking of Reversible CircuitsFeng-Jie Chao, Yung-Chih Chen. 646-653 [doi]
• Supporting Pipelined Memory Accesses in Processor SynthesisEssien Taylor, Colin Schilf, Sebastian Phemister, Russ Joseph. 654-657 [doi]
• BNRV: A Lightweight SIMD Extension for Efficient BitNet Inference on RISC-V CPUsZijun Jiang, Yangdi Lyu. 658-665 [doi]
• Design and Evaluation of an N-Trace Compliant Hardware Tracer for RISC-V ProcessorsOmer Karslioglu, Ismail Akturk. 666-673 [doi]
• FlexIO: A Scalable IO Chiplet Architecture with Flexible Memory Controller MappingJunpei Huang, Haobo Xu, Ying Wang 0001, Yinhe Han 0001. 674-681 [doi]
• Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA ProcessorsFan Yang, Toru Koizumi 0001, Jun Li, Shu Sugita, Yuriko Yamauchi, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie. 682-689 [doi]
• XDMA: A Distributed, Extensible DMA Architecture for Layout-Flexible Data Movements in Heterogeneous Multi-Accelerator SoCsFanchen Kong, Yunhao Deng, Xiaoling Yi, Ryan Antonio, Marian Verhelst. 690-693 [doi]
• AceHomo: Accelerating Privacy Preserving Inference Through Dynamic Level AdjustmentHongyan Li, Jinkai Zhang, Hang Lu, Xiaowei Li 0001. 694-701 [doi]
• HyperDrone: An Accurate, Robust, Fast, and Energy-Efficient Approach for Drone ClassificationShriniwas Kulkarni, Flavio Ponzina, Tajana Rosing. 702-709 [doi]
• Access Frequency-Aware Storage Reduction for Deep Learning Recommendation ModelChia-Chun Wang, Chuan-Yao Lai, Ren-Shuo Liu. 710-717 [doi]
• Recommendation-Expert Framework for Fast and Adaptive Scheduling in Computing Power NetworkYu Chen, Wenli Zheng. 718-725 [doi]
• Oak: A Fault-Tolerant Shared-Memory System Atop Memory-Semantic FabricsZhaoxiang Huang, Jianqin Yan, Hao Chen, Jiaxin Li, Yiming Zhang 0003. 726-729 [doi]
• TLV-HGNN: Thinking Like a Vertex for Memory-Efficient HGNN InferenceDengke Han, Duo Wang, Mingyu Yan, Xiaochun Ye, Dongrui Fan. 730-737 [doi]
• SageSC: Accelerating GraphSAGE Minibatch Inference on Memory-Intensive GraphsYuchen Gui, Wei Yuan 0006, Qizhe Wu, Huawen Liang, Letian Zhao, Linfeng Tao, Zhongguang Xu, Xi Jin 0002. 738-745 [doi]
• In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM ChipsIsmail Emir Yüksel, Ataberk Olgun, F. Nisa Bostanci, Oguzhan Canpolat, Geraldo F. Oliveira, Mohammad Sadrosadati, A. Giray Yaglikçi, Onur Mutlu. 754-763 [doi]
• Adaptive ML-KEM: A Configurable HW-SW Architecture for Post-Quantum CryptographyWenkai Wang, Chao Liu, Zhe Sun, Lei Ju 0001, Zimeng Zhou. 764-767 [doi]
• FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property GenerationSudipta Paria, Aritra Dasgupta 0002, Dinesh Reddy Ankireddy, Prabuddha Chakraborty, Swarup Bhunia. 768-775 [doi]
• Tracing the Logic: Evaluating LLM Reasoning Paths in RTL GenerationMatthew DeLorenzo, Kevin Tieu, Jeyavijayan Rajendran. 776-781 [doi]
• MALLS: Multi-Agent LLMs for Synthetic Hardware Vulnerability Generation and DetectionJonti Talukdar, Agastya Seth, Sanmitra Banerjee, Farshad Firouzi, Krishnendu Chakrabarty. 782-789 [doi]
• CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP LeakageNowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar. 790-797 [doi]
• FlashMP: Fast Discrete Transform-Based Solver for Preconditioning Maxwell's Equations on GPUsHaoyuan Zhang, Yaqian Gao, Xinxin Zhang, Jialin Li, Runfeng Jin, Yidong Chen 0014, Feng Zhang, Wu Yuan 0002, Wenpeng Ma, Shan Liang, Jian Zhang, Zhonghua Lu. 798-806 [doi]
• MH-SpGEMM: Efficient Sparse General Matrix-Matrix Multiplication on Modern GPUs via Masking and Hashing Cooperative OptimizationShuang Yang, Yaobin Wang, Ling Li, Qian Peng, Qiong Yu. 807-814 [doi]
• TensTFM: Efficient Total Focusing Method for Ultrasonic Array Imaging on Dataflow AcceleratorsJieran Zhang, Bizhao Shi, Guojie Luo. 815-822 [doi]
• Design of an Online Surface Code Decoder Using Union-Find AlgorithmTakuya Kasamura, Junichiro Kadomoto, Hidetsugu Irie. 823-830 [doi]
• Early Termination with Activation Sign Prediction for Energy-Efficient CNN Inference Using Sum-of-Power-of-Two QuantizationEmir Eryilmaz, Selim Sandal, Ismail Akturk. 831-834 [doi]
• Sustainable Acceleration of Generative AI Neural Network Models with Silicon PhotonicsTharini Suresh, Salma Afifi, Sudeep Pasricha. 835-842 [doi]
• Toward Lifelong-Sustainable Electronic-Photonic AI Systems via Extreme Efficiency, Reconfigurability, and RobustnessZiang Yin, Hongjian Zhou, Chetan Choppali Sudarshan, Vidya A. Chhabria, Jiaqi Gu 0002. 843-850 [doi]
• SUSTAINPHOT: Sustainable Large-Scale AI Training Using Analog Silicon Photonic AcceleratorsDharanidhar Dang. 851-858 [doi]
• Scaling Up the Sustainability of Photonic Tensor Cores With Device-Circuit-Signaling Co-DesignIshan G. Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo. 859-866 [doi]
• Representation Learning for Digital Integrated Circuit Design AutomationPratik Shrestha, Ioannis Savidis. 867-871 [doi]
• Engineering Privacy at the Edge: A Practical Guide to Differential Privacy in System ArchitecturesOlivera Kotevska, Wenjun Yang, Eyhab Al-Masri. 872-875 [doi]