Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, Florida, USA, 20-22 January, 199 - researchr publication

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Michel Cosnard, Kemal Ebcioglu, Jean-Luc Gaudiot, editors, Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, Florida, USA, 20-22 January, 199. Volume A-23 of IFIP Transactions, North-Holland, 1993.

Conference: ifip10-31993

Abstract is missing.

Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop ProgramsJiang Wang, Christine Eisenbeis. 3-14

Software Pipelining: Petri Net PacemakerVicki H. Allan, M. Rajagopalan, Randall M. Lee. 15-26

Efficient Execution of Doacross Loops on Distributed Memory SystemsA. Zaafrani, Mabo Robert Ito. 27-38

Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD ArchitectureChris J. Newburn, Andrew S. Huang, John Paul Shen. 39-52

A New Loop Partition Method-ClusteringShaw-Yen Tseng, Chung-Ta King, Chuan Yi Tang. 53-64

Flow-sensitive Interprocedural Analysis Method for ParallelizationTakayoshi Iitsuka. 65-76

Code Generation for Multi-Threaded Architectures from Dataflow GraphsStephan Murer, Philipp Färber. 77-90

The Initial Performance of a Bottom-Up Clustering Algorithm for Dataflow GraphsWalid A. Najjar, Lucas Roh, A. P. Wim Böhm. 91-100

Synchronization and Parallelism Control in the BARDE Dataflow ProcessorH. Seebauer, Jörg Siemers. 105-116

The Instruction Set Architecture of the Inference Processor UNIRED IIKentaro Shimada, Hanpei Koike, Hidehiko Tanaka. 117-128

A Functional Data-flow Architecture Dedicated to Real-time Image ProcessingJocelyn Sérot, Georges Quénot, Bertrand Zavidovique. 129-140

DART: A Data-Driven Processor Architecture for Real-Time ComputingWilliam G. Farquhar, Paraskevas Evripidou. 141-152

Two Fundamental Limits on Dataflow MultiprocessingDavid E. Culler, Klaus E. Schauser, Thorsten von Eicken. 153-164

The Realities of Parallel Processing and Dataflow s Role in It: Lessons from the NASA HPCC ProgramThomas L. Sterling, Michael J. MacDonald. 165-176

Integrated Network Barriers for ::::D::::-Dimensional MeshesJon A. Solworth, Jerry Stamatopoulos. 179-190

Parallel Dimension Permutations on Star-GraphShahram Latifi. 191-201

On the Effectiveness of Interleaved Memories for Binary TreesRajendra V. Boppana. 203-214

Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW ArchitecturesG. Menez, Michel Auguin, Fernand Boéri, C. Carrière. 217-228

Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar ProcessorsSoo-Mook Moon, Kemal Ebcioglu, Ashok K. Agrawala. 229-242

URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW ArchitecturesDavid A. Berson, Rajiv Gupta, Mary Lou Soffa. 243-254

Data Flow Computing and the Conjugate Gradient MethodNorman Rubin. 257-264

Results of Parallel Implementations of the Selection Problem Using SisalMarc Daumas, Paraskevas Evripidou. 265-272

A Parallel Implementation of the Traveling Salesman Problem on a Sequent Symmetry MulitprocessorAndrew Sohn. 273-280

Exploring the Stream Data Type in SISAL and Other LanguagesAndrew L. Wendelborn, H. Garsden. 283-294

Mulitdimensional Streams Rooted in DataflowEdward A. Lee. 295-306

High Level Compiling for Low Level MachinesCiaran O Donnell. 309-320

Modeling Instruction-Level Parallelism for Software PipeliningAli-Reza Adl-Tabatabai, Thomas R. Gross, Guei-Yuan Lueh, James Reinders. 321-330

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