Abstract is missing.
- Automatic abstraction and fault tolerance in cortical microachitecturesAtif Hashmi, Hugues Berry, Olivier Temam, Mikko H. Lipasti. 1-10 [doi]
- FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar templateNiket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg. 11-22 [doi]
- CRIB: consolidated rename, issue, and bypassErika Gunadi, Mikko H. Lipasti. 23-32 [doi]
- FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashesRishi Agarwal, Josep Torrellas. 33-44 [doi]
- Virtualizing performance asymmetric multi-core systemsYoungjin Kwon, Changdae Kim, Seungryoul Maeng, Jaehyuk Huh. 45-56 [doi]
- Vantage: scalable and efficient fine-grain cache partitioningDaniel Sanchez, Christos Kozyrakis. 57-68 [doi]
- Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPsAsit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. 69-80 [doi]
- Bypass and insertion algorithms for exclusive last-level cachesJayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney. 81-92 [doi]
- Increasing the effectiveness of directory caches by deactivating coherence for private memory blocksBlas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato. 93-104 [doi]
- TLSync: support for multiple fast barriers using on-chip transmission linesJungju Oh, Milos Prvulovic, Alenka G. Zajic. 105-116 [doi]
- OUTRIDER: efficient memory latency tolerance with decoupled strandsNeal Clayton Crago, Sanjay J. Patel. 117-128 [doi]
- Exploring the tradeoffs between programmability and efficiency in data-parallel acceleratorsYunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic. 129-140 [doi]
- Prefetch-aware shared resource management for multi-core systemsEiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt. 141-152 [doi]
- Rebound: scalable checkpointing for coherent shared memoryRishi Agarwal, Pranav Garg, Josep Torrellas. 153-164 [doi]
- Demand-driven software race detection using hardware performance countersJoseph L. Greathouse, Zhiqiang Ma, Matthew I. Frank, Ramesh Peri, Todd M. Austin. 165-176 [doi]
- i-NVMM: a secure non-volatile main memory system with incremental encryptionSiddhartha Chhabra, Yan Solihin. 177-188 [doi]
- Crafting a usable microkernel, processor, and I/O system with strict and provable information flow securityMohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan Valamehr, Timothy E. Levin, Ben Hardekopf, Ryan Kastner, Frederic T. Chong, Timothy Sherwood. 189-200 [doi]
- Sampling + DMR: practical and low-overhead permanent fault detectionShuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Venkatraman Govindaraju, Marc de Kruijf, Karthikeyan Sankaralingam. 201-212 [doi]
- Releasing efficient beta cores to market earlySangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau. 213-222 [doi]
- CPPC: correctable parity protected cacheMehrtash Manoochehri, Murali Annavaram, Michel Dubois. 223-234 [doi]
- Energy-efficient mechanisms for managing thread context in throughput processorsMark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron. 235-246 [doi]
- SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threadingWing-Kei S. Yu, Ruirui C. Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh. 247-258 [doi]
- An abacus turn model for time/space-efficient reconfigurable routingBinzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li. 259-270 [doi]
- A case for globally shared-medium on-chip interconnectAaron Carpenter, Jianyun Hu, Jie Xu, Michael C. Huang, Hui Wu. 271-282 [doi]
- The impact of memory subsystem resource sharing on datacenter applicationsLingjia Tang, Jason Mars, Neil Vachharajani, Robert Hundt, Mary Lou Soffa. 283-294 [doi]
- Adaptive granularity memory systems: a tradeoff between storage efficiency and throughputDoe Hyun Yoon, Min Kyu Jeong, Mattan Erez. 295-306 [doi]
- SpecTLB: a mechanism for speculative address translationThomas W. Barr, Alan L. Cox, Scott Rixner. 307-318 [doi]
- Power management of online data-intensive servicesDavid Meisner, Christopher M. Sadler, Luiz André Barroso, Wolf-Dietrich Weber, Thomas F. Wenisch. 319-330 [doi]
- Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal managementSusmit Biswas, Mohit Tiwari, Timothy Sherwood, Luke Theogarajan, Frederic T. Chong. 331-340 [doi]
- Benefits and limitations of tapping into stored energy for datacentersSriram Govindan, Anand Sivasubramaniam, Bhuvan Urgaonkar. 341-352 [doi]
- Rapid identification of architectural bottlenecks via precise event countingJohn Demme, Simha Sethumadhavan. 353-364 [doi]
- Dark silicon and the end of multicore scalingHadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger. 365-376 [doi]
- Moguls: a model to explore the memory hierarchy for bandwidth improvementsGuangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen. 377-388 [doi]
- A case for heterogeneous on-chip interconnects for CMPsAsit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das. 389-400 [doi]
- Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guaranteesBoris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu. 401-412 [doi]
- DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chipSheng Ma, Natalie D. Enright Jerger, Zhiying Wang. 413-424 [doi]
- Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systemsAniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi. 425-436 [doi]
- The role of optics in future high radix switch designNathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn. 437-448 [doi]
- Scalable power control for many-core architectures running multi-threaded applicationsKai Ma, Xue Li, Ming Chen, Xiaorui Wang. 449-460 [doi]
- Energy-efficient cache design using variable-strength error-correcting codesAlaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu. 461-472 [doi]