Table of Contents

• LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local ComputingDongrui Li, Tomomasa Yamasaki, Aarthy Mani, Anh-Tuan Do, Niangjun Chen, Bo Wang 0020. 1-6 [doi]
• FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch GenerationMahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique 0001. 1-6 [doi]
• WeNet: Configurable Neural Network with Dynamic Weight-Enabling for Efficient InferenceJingxiao Ma, Sherief Reda. 1-6 [doi]
• A Multicore GNN Training AcceleratorSudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar. 1-6 [doi]
• Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge IntelligenceSepehr Tabrizchi, Shaahin Angizi, Arman Roohi. 1-6 [doi]
• Multi-Source Transfer Learning for Design Technology Co-OptimizationJakang Lee, Jaeseung Lee, SeongHyeon Park, Seokhyeong Kang. 1-6 [doi]
• Learning from Output Transitions: A Chosen Challenge Strategy for ML Attacks on PUFsChia-Chih Lin, Ming-Syan Chen. 1-6 [doi]
• PAIRS: Pruning-AIded Row-Skipping for SDK-Based Convolutional Weight Mapping in Processing-In-Memory ArchitecturesJohnny Rhe, Kang Eun Jeon, Jong Hwan Ko. 1-6 [doi]
• A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting Adaptive Model Configuration and Word Elimination for Language Understanding on Edge DevicesZexi Ji, HanRui Wang, Miaorong Wang, Win-San Khwa, Meng-Fan Chang, Song Han, Anantha P. Chandrakasan. 1-6 [doi]
• IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin MachinesOmar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik. 1-6 [doi]
• Automatic Generation of Structured Macros Using Standard Cells ‒ Application to CIMChristian Lanius, Jie Lou, Johnson Loh, Tobias Gemmeke. 1-6 [doi]
• ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized TransformersGamze Islamoglu, Moritz Scherer, Gianna Paulin, Tim Fischer 0001, Victor J. B. Jung, Angelo Garofalo, Luca Benini. 1-6 [doi]
• Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference ServicesErich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii. 1-6 [doi]
• AR-PIM: An Adaptive-Range Processing-in-Memory ArchitectureTeyuh Chou, Fernando García-Redondo, Paul N. Whatmough, Zhengya Zhang. 1-6 [doi]
• Bridging the Gap Between Spiking Neural Networks & LSTMs for Latency & Energy EfficiencyGourav Datta, Haoqin Deng, Robert Aviles, Zeyu Liu 0003, Peter A. Beerel. 1-6 [doi]
• iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot ProductShien Zhu, Shuo Huai, Guochu Xiong, Weichen Liu. 1-6 [doi]
• Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore SystemsGaurav Narang, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande. 1-6 [doi]
• RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation ModelsHeewoo Kim, Haojie Ye, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati. 1-6 [doi]
• Teleport: A High-Performance ShiftNet Hardware Accelerator with Fused Layer ComputationHyunmin Kim, Sungju Ryu. 1-6 [doi]
• Low Power Logic Obfuscation Through System Level Clock GatingDaniel Xing, Yuntao Liu 0001, Ankur Srivastava 0001. 1-6 [doi]
• Model-Driven Dataset Generation for Data-Driven Battery SOH ModelsKhaled Sidahmed Sidahmed Alamin, Francesco Daghero, Giovanni Pollo, Daniele Jahier Pagliari, Yukai Chen, Enrico Macii, Massimo Poncino, Sara Vinco. 1-6 [doi]
• Hardware Trojans in fdSOIChristian Lanius, Florian Freye, Shutao Zhang, Tobias Gemmeke. 1-6 [doi]
• Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine LearningQiankai Cao, Xi Chen, Jie Gu 0001. 1-6 [doi]
• Energy-Efficient ReRAM-Based ML Training via Mixed Pruning and Reconfigurable ADCChukwufumnanya Ogbogu, Soumen Mohapatra, Biresh Kumar Joardar, Janardhan Rao Doppa, Deuk Heo, Krishnendu Chakrabarty, Partha Pratim Pande. 1-6 [doi]
• Efficient Machine Learning on Encrypted Data Using Hyperdimensional ComputingYujin Nam, Minxuan Zhou, Saransh Gupta, Gabrielle De Micheli, Rosario Cammarota, Chris Wilkerson, Daniele Micciancio, Tajana Rosing. 1-6 [doi]
• Sky-NN: Enabling Efficient Neural Network Data Processing with Skyrmion Racetrack MemoryYong-Cheng Liaw, Shuo-Han Chen, Yuan-Hao Chang 0001, Yu-Pei Liang. 1-6 [doi]
• Digital Implementation of On-Chip Hebbian Learning for Oscillatory Neural NetworkEdgar Luhulima, Madeleine Abernot, Federico Corradi, Aida Todri-Sanial. 1-6 [doi]
• Joint Optimization of Cache Management and Graph Reordering for GCN AccelerationKyeong-Jun Lee, Byungjun Kim, Han-Gyeol Mun, SeungHyun Moon, Jae-Yoon Sim. 1-6 [doi]
• CoolDRAM: An Energy-Efficient and Robust DRAMNezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad. 1-6 [doi]
• Processing-in-Memory Using Optically-Addressed Phase Change MemoryGuowei Yang, Cansu Demirkiran, Zeynep Ece Kizilates, Carlos A. Ríos Ocampo, Ayse K. Coskun, Ajay Joshi. 1-6 [doi]
• Temperature-Aware Memory Mapping and Active Cooling of Neural Processing UnitsVahidreza Moghaddas, Hammam Kattan, Tim Bücher, Mikail Yayla, Jian-Jia Chen, Hussam Amrouch. 1-6 [doi]
• Energy Efficient Real-Time Scheduling on Heterogeneous Architectures with Self-SuspensionWenwen Xu, Zheyu Zhang, Yuankai Xu, Jing Li, Yehan Ma, Yier Jin, Christopher D. Gill, Xuan Zhang 0001, An Zou. 1-6 [doi]
• TensorCV: Accelerating Inference-Adjacent Computation Using Tensor ProcessorsDongho Ha, Won Woo Ro, Hung-Wei Tseng 0001. 1-6 [doi]
• A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology NodeSandra Maria Shaji, Lingjun Zhu, Jun-Sik Yoon, Sung Kyu Lim. 1-6 [doi]
• Energy-Harvesting-Aware Adaptive Inference of Deep Neural Networks in Embedded SystemsGwanjong Park, Osama Khan, Euiseong Seo. 1-6 [doi]
• Partial-Sum Quantization for Near ADC-Less Compute-In-Memory AcceleratorsUtkarsh Saxena, Kaushik Roy 0001. 1-6 [doi]
• Quantifying the Overheads of Modular MultiplicationDeepraj Soni, Mohammed Nabeel 0001, Negar Neda, Ramesh Karri, Michail Maniatakos, Brandon Reagen. 1-6 [doi]
• Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPUJina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram. 1-6 [doi]
• Weight-Aware Activation Mapping for Energy-Efficient Convolution on PIM ArraysKang Eun Jeon, Johnny Rhe, Hyeonsu Bang, Jong Hwan Ko. 1-6 [doi]
• Energy-Efficient Missing Data Recovery in Wearable Devices: A Novel Search-Based ApproachDina Hussein, Taha Belkhouja, Ganapati Bhat, Janardhan Rao Doppa. 1-6 [doi]
• Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned TransformersJung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, Youngjoo Lee. 1-6 [doi]
• A Self-Powered Predictive Maintenance System Based on Piezoelectric Energy Harvesting and TinyMLZijie Chen, Yiming Gao 0009, Junrui Liang. 1-6 [doi]
• DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based SchedulerYiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma 0002, Le Ye, Tianyu Jia. 1-6 [doi]
• CARMA: Context-Aware Runtime Reconfiguration for Energy-Efficient Sensor FusionYifan Zhang, Arnav Vaibhav Malawade, Xiaofang Zhang, Yuhui Li, DongHwan Seong, Mohammad Abdullah Al Faruque, Sitao Huang. 1-6 [doi]
• RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to PositHyun Woo Oh, SeongMo An, Won-Sik Jeong, Seung Eun Lee. 1-6 [doi]
• Enabling Highly-Efficient DNA Sequence Mapping via ReRAM-based TCAMYu-Shao Lai, Shuo-Han Chen, Yuan-Hao Chang. 1-6 [doi]
• Energy-Efficient Machine Learning Acceleration: From Technologies to Circuits and SystemsChukwufumnanya Ogbogu, Madeleine Abernot, Corentin Delacour, Aida Todri-Sanial, Sudeep Pasricha, Partha Pratim Pande. 1-8 [doi]
• Multi-Objective Optimization for Floating Point Mix-Precision TuningZeqing Li, Yongwei Wu, Youhui Zhang. 1-6 [doi]
• Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN InferenceMatteo Risso, Alessio Burrello, Giuseppe Maria Sarda, Luca Benini, Enrico Macii, Massimo Poncino, Marian Verhelst, Daniele Jahier Pagliari. 1-6 [doi]
• Machine Learning Driven Synthesis of Clock GatingDoyeon Won, Soomin Kim, Taewhan Kim. 1-6 [doi]
• Scaled Population Division for Approximate ComputingKunal Bharathi, Sunil P. Khatri, Jiang Hu. 1-6 [doi]
• Cryogenic CMOS as an Enabler for Low Power Dynamic LogicRakshith Saligram, Suman Datta, Arijit Raychowdhury. 1-6 [doi]
• REFROM: Responsive, Energy-Efficient Frame Rendering for Mobile DevicesTsung-Yen Hsu, Yi-Shen Chen, Yun-Chih Chen, Yuan-Hao Chang, Tei-Wei Kuo. 1-6 [doi]
• Efficient Multi-Objective Optimization for PVT Variation-Aware Circuit Sizing Using Surrogate Models and Smart Corner SamplingOctavian Pascu, Catalin Visan, Georgian Nicolae, Mihai Boldeanu, Horia Cucu, Cristian Diaconu, Andi Buzo, Georg Pelz. 1-6 [doi]