Table of Contents

• Advanced Circuit Technology to Realize Post Giga-bit DRAMTakashi Okuda. 2-5 [doi]
• Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic CircuitsToshio Baba, Tetsuya Uemura. 7-12 [doi]
• Ultrafast Ternary Quantizer using Resonant Tunneling DevicesToshihiro Itoh, Takao Waho, K. Maezawa, Masafumi Yamamoto. 13-18 [doi]
• A Josephson Ternary Memory CircuitMititada Morisue, Jun Endo, Toshimitu Morooka, Nobuhiro Shimizu, Masahiro Sakamoto. 19-24 [doi]
• Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell ArraysNing Song, Marek A. Perkowski. 32-37 [doi]
• Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAsYasunori Nagata, D. Michael Miller, Masao Mukaidono. 38 [doi]
• Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision DiagramsHafiz Md. Hasan Babu, Tsutomu Sasao. 45-51 [doi]
• Implementing a Multiple-Valued Decision Diagram PackageD. Miller, Rolf Drechsler. 52-57 [doi]
• Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks SynthesisLuca Macchiarulo, Pierluigi Civera. 58 [doi]
• The MacLaurin s and Taylor s Series Expansions of the Symbolic Multiple Valued Logic FunctionsH. Chung, S. Pi, S. Rey. 65-70 [doi]
• A Characterization of r-Valued Functions Monotonic in an Order Based on RegularityNoboru Takagi, Akimitsu Hon-nami, Kyoichi Nakashima. 71-76 [doi]
• Some Results on the Decision for Sheffer Functions in Partial K-Valued Logic(II)Renren Liu. 77 [doi]
• On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and LabelsJon T. Butler, Tsutomu Sasao. 83-88 [doi]
• Evolutionary Methods in the Design of Quaternery Digital CircuitsClaudio Moraga, Wenjun Wang. 89-94 [doi]
• Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker ExpressionsPer Lindgren, Rolf Drechsler, Bernd Becker. 95 [doi]
• Multiple-Valued Logics for Theorem-Proving in First Order Logic with EqualityRobert J. Bignall, Matthew Spinks. 102-107 [doi]
• Compact Propositional Gödel LogicsMatthias Baaz, Richard Zach. 108-113 [doi]
• Many-Valued and Annotated Modal LogicsSeiki Akama, Jair Minoro Abe. 114 [doi]
• Application of Neuron-MOS to Current-Mode Multi-Valued Logic CircuitsJing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang. 128-133 [doi]
• Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential LogicTakahiro Hanyu, Takahiro Saito, Michitaka Kameyama. 134-139 [doi]
• Set-Valued Logic Circuits for Next Generation VLSI ArchitecturesTakafumi Aoki, Tatsuo Higuchi. 140-147 [doi]
• Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal SequencesYasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi. 148 [doi]
• Image Segmentation Based on Kleene AlgebraYutaka Hata, Makoto Ishikawa, Naotake Kamiura. 155-160 [doi]
• Learning with Permutably Homogenous Multiple-Valued Multiple-Threshold PerceptronsAlioune Ngom, Corina Reischer, Dan A. Simovici, Ivan Stojmenovic. 161-166 [doi]
• An Error Reducing Approach to Machine Learning using Multi-Valued Functional DecompositionCraig M. Files, Marek A. Perkowski. 167-172 [doi]
• Multi-Valued Functional Decomposition as a Machine Learning MethodCraig M. Files, Marek A. Perkowski. 173 [doi]
• Reed-Muller-Fourier versus Galois Field Representations of Four-Valued Logic FunctionsRadomir S. Stankovic, Dragan Jankovic, Claudio Moraga. 186-191 [doi]
• A Synthesis Method of the Approximate Reasoning Engine by means of Genetic AlgorithmY. Yamamoto. 201-208 [doi]
• Minimization of Multivalued Multithreshold Perceptrons using Genetic AlgorithmsAlioune Ngom, Ivan Stojmenovic, Zoran Obradovic. 209-214 [doi]
• Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic AlgorithmMartin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker. 215 [doi]
• On Low Cost Realization of Multiple-Valued Logic FunctionsTakahiro Hozumi, Osamu Kakusho, Yutaka Hata. 233-238 [doi]
• Multiple-Valued Logic Minimization using Universal Literals and Cost TablesBlair Fraser, Gerhard W. Dueck. 239-244 [doi]
• A Frontier Algorithm for Optimization of Multiple-Valued Logic FunctionsMostafa I. Abd-El-Barr, Muhammad M. Abd-El-Barr. 245-249 [doi]
• e-Bases of Triadic Logic OperationsGrant Pogosyan, T. Nakamura. 251-256 [doi]
• Functional Entropy and Decision TreesV. Cheushev, Vlad P. Shmerko, Dan A. Simovici, Svetlana N. Yanushkevich. 257 [doi]
• Look-up Tables (LUTs) for Multiple-Valued, Combinational LogicAli Sheikholeslami, R. Yoshimura, P. Glenn Gulak. 264-269 [doi]
• Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSITakahiro Hanyu, Kaname Teranishi, Michitaka Kameyama. 270-275 [doi]
• Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic CircuitsShugang Wei, Kensuke Shimizu. 276-281 [doi]
• Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic CircuitsKatsuhiko Shimabukuro, C. Zukeran. 282 [doi]
• Minimization of Incompletely Specified Regular Ternary Logic Functions and its Application to Fuzzy Switching FunctionsTomoyuki Araki, Hisayuki Tatsumi, Masao Mukaidono, F. Yamamoto. 289-296 [doi]
• Upper and Lower Bounds on the Number of Fuzzy/c Switching FunctionsHisayuki Tatsumi, Tomoyuki Araki, Masao Mukaidono, Shinji Tokumasu. 297-303 [doi]
• On Closure Operators in Fuzzy Deductive Systems and Fuzzy AlgebrasHelmut Thiele. 304-309 [doi]
• A Study on Operations in Interval and Paired ProbabilitiesYukari Yamauchi, Masao Mukaidono. 310 [doi]
• Functional-Device-Based VLSI for Intelligent Electronic SystemsTadashi Shibata. 317 [doi]
• A Novel Nonlinear Synapse Neuron Model Guaranteeing a Global Minimum - Wavelet NeuronTakeshi Yamakawa. 335 [doi]
• Data Envelopment Analysis using Fuzzy ConceptCengiz Kahraman, Ethem Tolga. 338-343 [doi]
• A Proposal and an Application of a Career-Mode Membership FunctionF. Wakui, M. Hirano. 344-349 [doi]
• Membership Functions in Automatic Harmonization SystemMasataka Tokumaru, K. Yamashita, Noriaki Muranaka, Shigeru Imanishi. 350-355 [doi]
• On Concurrent Tests of Fuzzy ControllersNaotake Kamiura, Yutaka Hata, Kazuharu Yamato. 356 [doi]
• Generating Sets for Clones and Partial ClonesFerdinand Börner, Lucien Haddad. 363-368 [doi]
• On Partial Clones Containing All Idempotent Partial OperationsJean Fugère, Lucien Haddad. 369-373 [doi]
• Some Continuous Maps on the Space of Clones in Multiple-Valued LogicHajime Machida. 374-379 [doi]
• A Finite Basis of the Set of All Monotone Partial Functions Defined over a Finite PosetAkihiro Nozaki, Vaktang Lashkia. 380-382 [doi]