Abstract is missing.
- Accelerating architecture researchJoel S. Emer. [doi]
- Performance analysis in the real world of on line servicesDileep Bhandarkar. [doi]
- Differentiating the roles of IR measurement and simulation for power and temperature-aware designWei Huang, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan. 1-10 [doi]
- User- and process-driven dynamic voltage and frequency scalingBin Lin, Arindam Mallik, Peter A. Dinda, Gokhan Memik, Robert P. Dick. 11-22 [doi]
- Accuracy of performance counter measurementsDmitrijs Zaparanuks, Milan Jovic, Matthias Hauswirth. 23-32 [doi]
- GARNET: A detailed on-chip network model inside a full-system simulatorNiket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha. 33-42 [doi]
- Cetra: A trace and analysis framework for the evaluation of Cell BE systemsJulio Merino, Lluc Alvarez, Marisa Gil, Nacho Navarro. 43-52 [doi]
- Zesto: A cycle-level simulator for highly detailed microarchitecture explorationGabriel H. Loh, Samantika Subramaniam, Yuejian Xie. 53-64 [doi]
- Lonestar: A suite of parallel irregular programsMilind Kulkarni, Martin Burtscher, Calin Cascaval, Keshav Pingali. 65-76 [doi]
- Exploring speculative parallelism in SPEC2006Venkatesan Packirisamy, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew, Tin-Fook Ngai. 77-88 [doi]
- Machine learning based online performance prediction for runtime parallelization and task schedulingJiangtian Li, Xiaosong Ma, Karan Singh, Martin Schulz, Bronis R. de Supinski, Sally A. McKee. 89-100 [doi]
- WARP: Enabling fast CPU scheduler development and evaluationHaoqiang Zheng, Jason Nieh. 101-112 [doi]
- CMPSched im: Evaluating OS/CMP interaction on shared cache managementJaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer, Ramesh Illikkal, Donald Newell, Srihari Makineni. 113-122 [doi]
- Understanding the cost of thread migration for multi-threaded Java applications running on a multicore platformQiming Teng, Peter F. Sweeney, Evelyn Duesterwald. 123-132 [doi]
- The data-centricity of Web 2.0 workloads and its impact on server performanceMoriyoshi Ohara, Priya Nagpurkar, Yohei Ueda, Kazuaki Ishizaki. 133-142 [doi]
- Characterizing and optimizing the memory footprint of de novo short read DNA sequence assemblyJeffrey J. Cook, Craig B. Zilles. 143-152 [doi]
- An analytic model of optimistic Software Transactional MemoryArmin Heindl, Gilles Pokam, Ali-Reza Adl-Tabatabai. 153-162 [doi]
- Analyzing CUDA workloads using a detailed GPU simulatorAli Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt. 163-174 [doi]
- Evaluating GPUs for network packet signature matchingRandy Smith, Neelam Goyal, Justin Ormont, Karthikeyan Sankaralingam, Cristian Estan. 175-184 [doi]
- Online compression of cache-filtered address tracesPierre Michaud. 185-194 [doi]
- Analysis of the TRIPS prototype block predictorNitya Ranganathan, Doug Burger, Stephen W. Keckler. 195-206 [doi]
- Experiment flows and microbenchmarks for reverse engineering of branch predictor structuresVladimir Uzelac, Aleksandar Milenkovic. 207-217 [doi]
- Analyzing the impact of on-chip network traffic on program phases for CMPsYu Zhang, Berkin Özisikyilmaz, Gokhan Memik, John Kim, Alok N. Choudhary. 218-226 [doi]
- SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly codeJeff Ringenberg, Trevor N. Mudge. 227-237 [doi]
- Accurately approximating superscalar processor performance from tracesKiyeon Lee, Shayne Evans, Sangyeun Cho. 238-248 [doi]
- QUICK: A flexible full-system functional modelDam Sunwoo, Joonsoo Kim, Derek Chiou. 249-258 [doi]