Abstract is missing.
- Towards Designing and Deploying Ising MachinesSachin S. Sapatnekar. 1 [doi]
- GOALPlace: Begin with the End in MindAnthony Agnesina, Rongjian Liang, Geraldo Pradipta, Anand Rajaram, Haoxing Ren. 2-10 [doi]
- Invited: Scaling Standard Cell Layout Using Track Height Compression and Design Technology Co-optimizationChung-Kuan Cheng, Byeonggon Kang, Bill Lin 0001, Yucheng Wang. 11-19 [doi]
- Invited: Physical Design Challenges for Design Technology Co-optimizationTaewhan Kim. 20-21 [doi]
- LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian MethodJing Mai, Chunyuan Zhao, Zuodong Zhang, Zhixiong Di, Yibo Lin, Runsheng Wang, Ru Huang 0001. 22-30 [doi]
- Cypress: VLSI-Inspired PCB Placement with GPU AccelerationNiansong Zhang, Anthony Agnesina, Noor Shbat, Yuval Leader, Zhiru Zhang, Haoxing Ren. 31-41 [doi]
- GPU-Accelerated Inverse Lithography Towards High Quality Curvy Mask GenerationHaoyu Yang, Haoxing Ren. 42-50 [doi]
- Invited: Trailblazing the Future: Innovative Chip Design in the Era of Pervasive AISudipto Kundu. 51 [doi]
- Invited: Automatic Die-to-Die Routing with ShieldingSheng-Yu Hsiao, Yu-Yueh Chang, Jeong-Tying Li. 52-53 [doi]
- Invited: Streamlining and Automating Routing of Multi-Chiplet TechnologiesKsenia Roze. 54 [doi]
- ML-QLS: Multilevel Quantum Layout SynthesisWan-Hsuan Lin, Jason Cong. 55-63 [doi]
- LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated CircuitsHongjian Zhou, Keren Zhu 0004, Jiaqi Gu 0002. 64-72 [doi]
- Invited: Physical Design for Systolic Array-Based Integrated CircuitsJiang Hu. 73 [doi]
- Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design MethodologyMeizhi Wang, Yi-Ru Chen, S. S. Teja Nibhanupudi, Elham Amini, Antonio Saavedra, Yinan Wang, Daniel Wasserman, Jean-Pierre Seifert, Jaydeep P. Kulkarni. 74-82 [doi]
- Multi-Stage CSM Timing Waveform Propagation Accelerated by NLDM AssistanceShih-Kai Lee, Pei-Yu Lee, Iris Hui-Ru Jiang. 83-90 [doi]
- Invited: The Future of Functional ECO Automation and Logical Equivalence Checking for Advanced Digital Design FlowsZhuo Li 0001, David Stratman. 91-92 [doi]
- Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA ResearchVidya A. Chhabria, Jiang Hu, Andrew B. Kahng, Sachin S. Sapatnekar. 93-101 [doi]
- Invited: Mapping Two Decades of Innovation: Lessons from 25 Years of ISPD ResearchGona Rahmaniani, Matthew Guthaus, Laleh Behjat. 102-110 [doi]
- Invited: How Automotive Functional Safety is Disrupting Digital ImplementationChuck J. Alpert, Vitali Karasenko, Connie O'Shea. 111-115 [doi]
- HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph LearningYuan Pu 0001, Fangzhou Liu, Zhuolun He, Keren Zhu 0001, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu 0001. 116-124 [doi]
- GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected DelaysFangzhou Liu, Guannan Guo, Yuyang Ye 0001, Ziyi Wang, Wenjie Fu 0003, Weihua Sheng, Bei Yu 0001. 125-133 [doi]
- Invited: AI-assisted RoutingQijing Wang, Liang Xiao, Evangeline F. Y. Young. 134-142 [doi]
- DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous AgentChen-Chia Chang, Chia-Tung Ho, Yaguang Li, Yiran Chen 0001, Haoxing Ren. 143-151 [doi]
- LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced NodesYi-Chen Lu, Kishor Kunal, Geraldo Pradipta, Rongjian Liang, Ravikishore Gandikota, Haoxing Ren. 152-162 [doi]
- Invited: Artificial Netlist Generation for Enhanced Circuit Data AugmentationSeokhyeong Kang. 163 [doi]
- Cell-Flex Metrics for Designing Optimal Standard Cell Layout with Enhanced Cell Layout FlexibilityByeonggon Kang, Ying Yuan, Yucheng Wang, Bill Lin 0001, Chung-Kuan Cheng. 164-172 [doi]
- Scalable CFET Cell Library Synthesis with A DRC-Aware Lookup Table to Optimize Valid Pin AccessTing-Wei Lee, Ting Xin Lin, Yih-Lang Li. 173-181 [doi]
- LVFGen: Efficient Liberty Variation Format (LVF) Generation Using Variational Analysis and Active LearningJunzhuo Zhou, Haoxuan Xia, Wei W. Xing, Ting-Jung Lin, Li Huang, Lei He 0001. 182-190 [doi]
- Abuttable Analog Cell Library and Automatic AMS LayoutTianjia Zhou, Cheng Chang, Li Huang, Jingyun Gu, Zexin Ji, Xiangyang Liu, Hailang Liang, Zhanfei Chen, Ting-Jung Lin, Song Wang, Na Bai, Zhengping Li, Lei He. 191-199 [doi]
- Placement-Aware 3D Net-to-Pad Assignment for Array-Style Hybrid Bonding 3D ICsPruek Vanna-Iampikul, Jun-Sik Yoon, Chaeryung Park, Gary Yeap, Sung Kyu Lim. 200-208 [doi]
- Invited: Physical Design for Advanced 3D ICs: Challenges and SolutionsYuxuan Zhao 0001, Lancheng Zou, Bei Yu 0001. 209-216 [doi]
- Invited: Chiplet-Based Integration - Scale-Down and Scale-OutBoris Vaisband. 217 [doi]
- Invited: Innovation in Times of Technology DisruptionBryan Preas. 218-219 [doi]
- Invited: Shaping the Future of Interconnected Physical DesignDavid Z. Pan. 220-221 [doi]
- Invited: Coping with InterconnectsJason Cong. 222-230 [doi]
- Invited: Automation and Optimization of Heterogeneous Multi-Die SystemsHenry Sheng. 231-232 [doi]
- ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICsZheng Yang, Zhen Zhuang, Bei Yu 0001, Tsung-Yi Ho, Martin D. F. Wong, Sung Kyu Lim. 233-241 [doi]
- Invited: Modeling and Design Methodology for Backside Integration of Voltage ConvertersAmaan Rahman, Hang Yang, Cong Hao, Sung Kyu Lim. 242-250 [doi]
- Invited: Next-Generation Power Integrity Concepts and Applications for Physical DesignEmrah Acar. 251 [doi]
- Invited: ISPD 2025 Performance-Driven Large Scale Global Routing ContestRongjian Liang, Anthony Agnesina, Wen-Hao Liu 0001, Matt Liberty, Hsin-Tzu Chang, Haoxing Ren. 252-256 [doi]