Abstract is missing.
- Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG RunYi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy. 1-6 [doi]
- Efficient Cell-Aware Defect Characterization for Multi-bit CellsRuifeng Guo, Brian Archer, Kevin Chau, Xiaolei Cai. 7-12 [doi]
- Automatic Generation of In-Circuit Tests for Board Assembly DefectsHarm van Schaaijk, Martien Spierings, Erik Jan Marinissen. 13-18 [doi]
- RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error CorrectionJia-Yun Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu. 19-24 [doi]
- MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing SystemDesong Pang, Dawen Xu 0002, Ying Wang, Huaguo Liang. 25-30 [doi]
- DVFS Binning Using Machine-Learning TechniquesKeng-Wei Chang, Chun-Yang Huang, Szu-Pang Mu, Jian-min Huang, Shi-Hao Chen, Mango C.-T. Chao. 31-36 [doi]
- Periodic Online LBIST Considerations for a Multicore ProcessorTeresa L. McLaurin. 37-42 [doi]
- Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and SolutionsVenkat Yellapragada, Suresh Raman, Banadappa Shivaray, Luc Romain, Benoit Nadeau-Dostie, Martin Keim, Jean-Francois Cote, Albert Au, Giri Podichetty, Ashok Anbalan. 43-48 [doi]
- Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout TechniqueAibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo. 49-54 [doi]
- A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan NetworksRiccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero. 55-60 [doi]
- An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining MetricsTara Ghasempouri, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik. 61-66 [doi]
- Skew-Aware Functional Timing Analysis Against Setup Violation for Post-Layout ValidationPin-Ru Jhao, Denny C.-Y. Wu, Charles H.-P. Wen. 67-72 [doi]
- Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processorsYing Wang, Wen Li, Huawei Li, Xiaowei Li. 73-78 [doi]
- Grey Zone in Pre-Silicon Hardware Trojan DetectionJing Ye, Yipei Yang, Yue Gong, Yu Hu, Xiaowei Li. 79-84 [doi]
- Small Trojan Testing Using Bounded Model CheckingYing Zhang, Lu Yu, Huawei Li, Jianhui Jiang. 85-90 [doi]
- Low-Distortion One-Tone and Two-Tone Signal Generation Using AWG Over Full Nyquist RegionTomonori Yanagida, Shohei Shibuya, Kosuke Machida, Koji Asami, Haruo Kobayashi. 91-96 [doi]
- Accurate Spectral Testing with Impure Test Stimulus for Multi-tone TestYuming Zhuang, Degang Chen. 97-102 [doi]
- Cost-Effective High Purity Signal Generator Using Pre-distortionYuming Zhuang, Degang Chen. 103-108 [doi]
- Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT ArchitecturesGuoliang Li 0004, Henry Zhao, Qinfu Yang, Jun Qian, Yu Huang. 109-114 [doi]
- Good Die Prediction Modelling from Limited Test ItemsTakeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura. 115-120 [doi]
- X-Sources Analysis for Improving the Test QualityKun-Han Tsai. 121-126 [doi]
- Error Indication Signal Collapsing for Implication-Based Concurrent Error DetectionChih-Hao Wang, Chi-Hsuan Ho, Tong-Yu Hsieh. 127-132 [doi]
- A No-Reference Error-Tolerability Test Methodology for Image Processing ApplicationsTong-Yu Hsieh, Chao-Ru Chen. 133-138 [doi]
- A Hierarchical Approach for Devising Area Efficient Concurrent Online CheckersBehrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, Jaan Raik, Gert Jervan. 139-144 [doi]
- Balancing Testability and Security by Configurable Partial Scan DesignXi Chen, Omid Aramoon, Gang Qu, Aijiao Cui. 145-150 [doi]
- A Comprehensive Security System for Digital Microfluidic BiochipsChun-Yu Lin, Juinn-Dar Huang, Hailong Yao, Tsung-Yi Ho. 151-156 [doi]