Table of Contents

• FPGA Implementation of Stair Matrix based Massive MIMO DetectionShahriar Shahabuddin, Mahmoud A. M. Albreem, Mohammad Shahanewaz Shahabuddin, Zaheer Khan 0001, Markku J. Juntti. 1-4 [doi]
• Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog ConvertersPatrick Valet, David Schwingshackl, Andrea M. Tonello. 1-4 [doi]
• Ultra Low Power < 9 nW Adaptive Duty Cycling Oscillator in 22 nm FDSOI CMOS Technology using Back Gate BiasingBastian Lindner, Niko Joram, Frank Ellinger. 1-4 [doi]
• Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware ArchitecturesPedro T. L. Pereira, Guilherme Paim, Guilherme Ferreira, Eduardo A. C. da Costa, Sérgio J. M. Almeida, Sergio Bampi. 1-4 [doi]
• Current Behavior on Process Variability Aware FinFET Inverter DesignsLeonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001. 1-4 [doi]
• EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD ProcessorsMariana C. Toledo, Sandro M. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon. 1-4 [doi]
• Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF CommunicationsGuillermo Royo, Antonio D. Martínez-Pérez, C. Sánchcz-Azqueta, Concepción Aldea, Santiago Celma. 1-4 [doi]
• An ISM-Band Multi-Phase Injection-Locked Ring OscillatorMustafa Sedat Berk, Benan Beril Inam, Mustafa Berke Yelten. 1-4 [doi]
• New Low-Power Architectures of Support Vector Machine Classifier for Speech Recognition SystemGracieth Cavalcanti Batista, Duarte Lopes de Oliveira, Osamu Saotome. 1-4 [doi]
• Chronos: An Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic DistributionGeaninne Lopes, Iaçanã I. Weber, César A. M. Marcon, Fernando Gehm Moraes. 1-4 [doi]
• TailoredCore: Generating Application-Specific RISC-V-based CoresJeferson González-Gómez, Steven Ávila-Ardón, Jonathan Rojas-González, Andres Stephen-Cantillano, Jorge Castro-Godínez, Carlos Salazar-García, Muhammad Shafique 0001, Jörg Henkel. 1-4 [doi]
• Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta ModulatorsMarco Orna, Dominique Morche, Andrea Baschirotto, Emmanuel Allier, Patrick Arno. 1-4 [doi]
• Design Considerations for the Development of Computational Resistive MemoriesFelipe Pinto, Ioannis Vourkas. 1-4 [doi]
• On the Possibility to Use Energy Harvesting on Beta Radiation in Nuclear EnvironmentsAlexandre Quenon, Evelyne Daubie, Véronique Moeyaert, Fortunato Carlos Dualibe. 1-4 [doi]
• Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain CircuitsArijit Karmakar, Valentijn De Smedt, Paul Leroux. 1-4 [doi]
• Benchmarking Open Access VLSI Partitioning ToolsIsadora Oliveira, Marcelo Danigno, Paulo F. Butzen, Ricardo Reis 0001. 1-4 [doi]
• Design of a Constant Current Laser Driver for Biomedical ApplicationsÖzgür Deniz Temel, Onur Ferhanoglu, Mustafa Berke Yelten. 1-4 [doi]
• A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS ProcessNisha Gupta, Ashudeb Dutta, Shiv Govind Singh. 1-4 [doi]
• On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache MemorySheetal Barekar, Madan Mali. 1-4 [doi]
• Design and implementation of a trans-impedance amplifier for a miniaturized saturated absorption spectrometerKevin Sosa, Horacio Failache, Julián Oreggioni. 1-4 [doi]
• Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-FlopsOliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler 0001, Milos Krstic. 1-4 [doi]
• A CMOS Implementation of the Tent Map for Random Number GenerationMuhammed Mustafa Kizmaz, Salih Ergün. 1-4 [doi]
• A Strategy to Achieve Competitive Performance in Basic RF LNAsAntonio D. Martínez-Pérez, Pedro A. Martínez-Martínez, Francisco Aznar, Guillermo Royo, Santiago Celma. 1-4 [doi]
• On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with MismatchAna C. A. Barbosa, Juan C. Castellanos. 1-4 [doi]
• Residual Impedance Impact on MAX30001 Accuracy for Bioimpedance ApplicationsShelby Critcher, Todd J. Freeborn. 1-4 [doi]
• A Power-Efficient FFT Hardware Architecture Exploiting Approximate AddersGuilherme Ferreira, Pedro Tauã Lopes Pereira, Guilherme Paim, Eduardo A. C. da Costa, Sergio Bampi. 1-4 [doi]
• Reconfigurable E-band Receiver Development for Joint Communication and SensingSandra George, Padmanava Sen, André Noll Barreto, Gerhard P. Fettweis. 1-4 [doi]
• Hardware Trojan with Frequency ModulationAsh Luft, Mihai Sima, Michael McGuire. 1-4 [doi]
• FPGA Implementation of a New PUF Based on Galois Ring OscillatorsMiguel Garcia-Bosque, Guillermo Díez-Señorans, Carlos Sánchez-Azqueta, Santiago Celma. 1-4 [doi]
• A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution AcceleratorsLeonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory, Fernando Gehm Moraes. 1-4 [doi]
• Design methodology for 112Gb/s PAM4 Wireline ADC-Based ReceiversDavid Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin. 1-4 [doi]
• A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global CommunicationDuarte L. Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista. 1-4 [doi]
• An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent ReceiversÁlvaro Fernandez Bocco, Fredy Solis, Benjamin T. Reyes, Damian A. Morero, Mario R. Hueda. 1-4 [doi]
• Simulating large neural networks embedding MLC RRAM as weight storage considering device variationsMarkus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach. 1-4 [doi]
• High-speed Hardware Accelerator for Trace Decoding in Real-Time Program MonitoringAugusto W. Hoppe, Jürgen Becker 0001, Fernanda Lima Kastensmidt. 1-4 [doi]
• A 1V, 450pS OTA Based on Current-Splitting and Modified Series-Parallel MirrorsLuis Henrique Rodovalho, Rafael Sanchotene Silva, Cesar Ramos Rodrigues. 1-4 [doi]
• Analog and RF Circuit Constrained Optimization Using Multi-Objective Evolutionary AlgorithmsKostas Touloupas, Paul-Peter Sotiriadis. 1-4 [doi]
• Towards analog computing devices for matrix algebraic problemsMaide Bucolo, Arturo Buscarino, Luigi Fortuna, Mattia Frasca. 1-4 [doi]
• Study of a Voltage-Mode Readout Configuration for Micromachined CMOS Transistors for Uncooled IR SensingElisabetta Moisello, Michele Vaiana, Maria Eloisa Castagna, Giuseppe Bruno, Igor Brouk, Tanya Blank, Sharon Bar-Lev, Yael Nemirovsky, Piero Malcovati, Edoardo Bonizzoni. 1-4 [doi]
• Non-Memoryless vs. Memoryless Hardware Architectures for Convolutional Neural NetworksAlexandre B. Z. de França, Fernanda D. V. R. Oliveira, José Gabriel Rodríguez Carneiro Gomes, Nadia Nedjah. 1-4 [doi]
• A Library of High-Level Models for the Simulation of DC-DC ConvertersThomas Eleftherios Dimitrios Kizas, Lorenzo Crespi, Piero Malcovati, Andrea Baschirotto. 1-4 [doi]
• Robust Passive Coherent Location via Nonlinearly Constrained Least SquaresDaniel Patricio Nicolalde Rodríguez, José Antonio Apolinário, Wallace A. Martins. 1-4 [doi]
• ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip ApplicationsHugo Daniel Hernández, Diego Augusto Pontes, Tarciso A. Martins, David Reyes, Wilhelmus A. M. Van Noije. 1-4 [doi]
• High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary ComparatorRicardo Escobar, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza, Ramiro Taco. 1-4 [doi]
• A Brazilian Sign Language Gesture Recognizing System Using Gait Energy ImageL. Wesley Passos, Gabriel M. Araujo, Jonathan N. Gois, Amaro A. de Lima. 1-4 [doi]
• Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADCAbderrahmane Ghimouz, Fatah Rarbi, Olivier Rossetto. 1-4 [doi]
• Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video CodingLuiz Neto, Marcel Moscarelli Corrêa, Daniel Palomino 0001, Luciano Agostini, Guilherme Corrêa. 1-4 [doi]
• Line Resistance Impact in Memristor-based Multi Layer Perceptron for Pattern RecognitionFernando L. Aguirre, Sebastián Matías Pazos, Felix Palumbo, N. Gomez, Enrique Miranda 0002, Jordi Suñé. 1-4 [doi]
• The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet NetworkGeancarlo Abich, Ricardo Reis 0001, Luciano Ost. 1-4 [doi]
• Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDXDavid Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin. 1-4 [doi]
• Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based CircuitLeonardo H. Brendler, Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Cristina Meinhardt, Ricardo A. L. Reis. 1-4 [doi]
• A Wearable Wireless Sensing System for Capturing Human Arm MotionM. Agius, Clive Seguna, Judie Attard, Kris Scicluna, Jeremy Scerri. 1-4 [doi]
• RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologiesLionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco. 1-4 [doi]
• A JTAG-based Fault Emulation Platform for Dependability Analyses of Processor-based ASICsAndrea Floridia, Ernesto Sánchez 0001. 1-4 [doi]
• Estimating Cole-Impedance Parameters from Limited Frequency-Band Impedance MeasurementsTodd J. Freeborn, Shelby Critcher. 1-4 [doi]
• Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGACarolina Teng, Renan W. Achjian, Caio C. Braga, Marcelo Knörich Zuffo, Wang J. Chau. 1-4 [doi]
• Reliability Analysis in Less than 200 Lines of CodeAnselm Breitenreiter, Oliver Schrape, Marko S. Andjelkovic, Milos Krstic. 1-4 [doi]
• Soft Error Sensibility Window at FinFET DICE SRAMMaria Eduarda de Melo Hang, Cleiton M. Marques, Paulo F. Butzen, Cristina Meinhardt. 1-4 [doi]
• A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOSCarlos A. Pinheiro, Fabián Olivera, Antonio Petraglia. 1-4 [doi]
• Linearization for High-Speed Current-Steering DACs Using Neural NetworksDaniel Beauchamp, Keith M. Chugg. 1-4 [doi]
• Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation FactorsGordana Jovanovic-Dolecek, Jose M. de la Rosa. 1-4 [doi]
• Edge Computing Technique for a 87% Energy Saving for IoT Device Dedicated to Environmental MonitoringFrancois Rivet, Laura Foucaud, Guillaume Ferré. 1-4 [doi]
• Background Compensation of Frequency Interleaved DAC for Optical TransceiversAgustin C. Galetto, Benjamin T. Reyes, Damian A. Morero, Mario R. Hueda. 1-4 [doi]
• Assessment of key parameters in a microwave imaging system design for breast cancer detectionDavid Ponce, Alexandre de Jesus Aragão, Bruno Sanches, Wilhelmus A. M. Van Noije. 1-4 [doi]
• Monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysisLaura Hernández-Alpizar, Arys Carrasquilla-Batista, Lilliana Sancho-Chavarría. 1-4 [doi]