Abstract is missing.
- Modulo scheduling without overlapped lifetimesEric Stotzer, Ernst L. Leiss. 1-10 [doi]
- Synchronous objects with scheduling policies: introducing safe shared memory in lustrePaul Caspi, Jean-Louis Colaço, Léonard Gérard, Marc Pouzet, Pascal Raymond. 11-20 [doi]
- Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architecturesTaewook Oh, Bernhard Egger, Hyunchul Park, Scott A. Mahlke. 21-30 [doi]
- PTIDES on flexible task graph: real-time embedded systembuilding from theory to practiceJia Zou, Joshua S. Auerbach, David F. Bacon, Edward A. Lee. 31-40 [doi]
- A compiler optimization to reduce soft errors in register filesJongeun Lee, Aviral Shrivastava. 41-49 [doi]
- Raced profiles: efficient selection of competing compiler optimizationsHugh Leather, Michael F. P. O Boyle, Bruce Worton. 50-59 [doi]
- Eliminating the call stack to save RAMXuejun Yang, Nathan Cooprider, John Regehr. 60-69 [doi]
- Live-range unsplitting for faster optimal coalescingSandrine Blazy, Benoit Robillard. 70-79 [doi]
- Push-assisted migration of real-time tasks in multi-core processorsAbhik Sarkar, Frank Mueller, Harini Ramaprasad, Sibin Mohan. 80-89 [doi]
- Software transactional memory for multicore embedded systemsJennifer Mankin, David Kaeli, John Ardini. 90-98 [doi]
- Synergistic execution of stream programs on multicores with acceleratorsAbhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil. 99-108 [doi]
- Towards device emulation code generationThomas Heinz, Reinhard Wilhelm. 109-118 [doi]
- Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson. 119-128 [doi]
- Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoringPaul E. McKechnie, Michaela Blott, Wim Vanderbauwhede. 129-136 [doi]
- Tracing interrupts in embedded softwareGiovani Gracioli, Sebastian Fischmeister. 137-146 [doi]
- Addressing the challenges of DBT for the ARM architectureRyan W. Moore, José Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser. 147-156 [doi]
- Integrating hardware and software information flow analysesColin J. Fidge, Diane Corney. 157-166 [doi]
- Specification and verification of time requirements with CCSL and EsterelCharles André, Frédéric Mallet. 167-176 [doi]