Abstract is missing.
- Extending Verilator to Enable Fault SimulationEndri Kaja, Nicolas Ojeda Leon, Michael Werner, Bogdan-Andrei Tabacaru, Keerthikumara Devarajegowda, Wolfgang Ecker. 1-6 [doi]
- A Matter of Overhead - Response Time Analysis of Hard Real-Time Systems in Theory and PracticeMax Brand, Albrecht Mayer, Frank Slomka. 1-7 [doi]
- Exploration of DDR5 with the Open-Source Simulator DRAMSysLukas Steiner, Matthias Jung 0001, Norbert Wehn. 1-11 [doi]
- Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core ApplicationsMartín Letras, Joachim Falk, Jürgen Teich. 1-11 [doi]
- Comprehensive modeling and evaluation of Network-on-Chip performabilityJie Hou, Martin Radetzki. 1-12 [doi]
- APPEL - AGILA ProPErty and Dependency Description LanguageChristoph Grimm 0001, Frank Wawrzik, Alexander Louis-Ferdinand Jung, Konstantin Lübeck, Sebastian Post, Johannes Koch, Oliver Bringmann 0001. 1-11 [doi]
- On Self-Verifying DSL Generation for Embedded Systems AutomationZhao Han, Shahzaib Qazi, Michael Werner, Keerthikumara Devarajegowda, Wolfgang Ecker. 1-7 [doi]
- Constrained Random Verification for RISC-V: Overview, Evaluation and DiscussionSallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler. 1-8 [doi]
- ICP and IC3 with Stronger GeneralizationFelix Winterer, Tobias Seufert, Karsten Scheibler, Tino Teige, Chritsoph Scholl, Bernd Becker 0001. 1-12 [doi]
- Benchmarking SMT Solvers on Automotive CodeLukas Mentel, Karsten Scheibler, Felix Winterer, Bernd Becker 0001, Tino Teige. 1-10 [doi]
- Register and Instruction Coverage Analysis for Different RISC-V ISA ModulesPeer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt. 1-8 [doi]