Abstract is missing.
- Distributed O(N) Linear Solver for Dense Symmetric Hierarchical Semi-Separable MatricesChenhan D. Yu, Severin Reiz, George Biros. 1-8 [doi]
- Optimization of Numerous Small Dense-Matrix-Vector Multiplications in H-Matrix Arithmetic on GPUSatoshi Ohshima, Ichitaro Yamazaki, Akihiro Ida, Rio Yokota. 9-16 [doi]
- An Automatic MPI Process Mapping Method Considering Locality and Memory Congestion on NUMA SystemsMulya Agung, Muhammad Alfian Amrizal, Ryusuke Egawa, Hiroyuki Takizawa. 17-24 [doi]
- Performance Tuning of Tile Matrix DecompositionTomohiro Suzuki. 25-31 [doi]
- A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon CalibrationHayate Okuhara, Ryosuke Kazami, Hideharu Amano. 32-37 [doi]
- Multicore Power Estimation using Independent Component Analysis Based ModelingMark Sagi, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf. 38-45 [doi]
- Building Scalable and Highly Efficient Accelerators Near the End of Conventional ScalingJohannes Maximilian Kühn. 46-52 [doi]
- FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 BoardKoki Honda, Kaijie Wei, Hideharu Amano. 53-60 [doi]
- Design of Asynchronous CNN Circuits on Commercial FPGA from Synchronous CNN CircuitsHayato Kato, Hiroshi Saito. 61-67 [doi]
- Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAsAhmed Kamaleldin, Muhammad Ali, Pedram Amini Rad, Marcus Gottschalk, Diana Göhringer. 68-73 [doi]
- A Novel SLM-Based Virtual FPGA Overlay ArchitectureTheingi Myint, Motoki Amagasaki, Qian Zhao 0001, Masahiro Iida, Masato Kiyama. 74-80 [doi]
- Deep Learning Framework with Arbitrary Numerical PrecisionMasato Kiyama, Motoki Amagasaki, Masahiro Iida. 81-86 [doi]
- Tumour Detection using Convolutional Neural Network on a Lightweight Multi-Core DeviceT. Hui Teo, Wei Ming Tan, Yi Shu Tan. 87-92 [doi]
- Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural NetworksRyosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara. 93-100 [doi]
- Distributed Neural Networks using TensorFlow over Multicore and Many-Core SystemsJagadish Kumar Ranbirsingh, Hanke Kimm, Haklin Kimm. 101-107 [doi]
- An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGAKatsunoshin Matsui, Md. Ashraful Islam, Kenji Kise. 108-115 [doi]
- Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented ProgrammingTakeshi Ohkawa, Ikuta Tanigawa, Mikiko Sato, Kenji Hisazumi, Nobuhiko Ogura, Harumi Watanabe. 116-122 [doi]
- Implementation of Content-Based Anonymization Edge Router on NetFPGAAkihiro Fukuhara, Tomomu Iwai, Yuiko Sakuma, Hiroaki Nishi. 123-128 [doi]
- Unified Symbol Framework to Improve UI ComprehensionRentaro Yoshioka, Naoyuki Murata. 129-134 [doi]
- Smart Ontology-Based Event IdentificationSarika Jain, Archana Patel. 135-142 [doi]
- A Semi-Lossless Image Compression Procedure using a Lossless Mode of JPEGMd. Atiqur Rahman, Mohamed Hamada. 143-148 [doi]
- A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical SystemsMiguel Gorgues Alonso, José Flich, Meriem Turki, Davide Bertozzi. 149-156 [doi]
- Low-Cost Congestion Detection Mechanism for Networks-on-ChipZhengqian Han, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe. 157-163 [doi]
- A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCsJie Hou, Qi Han, Martin Radetzki. 164-171 [doi]
- Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-ChipMichael Conrad Meyer, Yu Wang 0064, Takahiro Watanabe. 172-179 [doi]
- Algorithm to Determine Extended Edit Distance between Program CodesKazuki Anzai, Yutaka Watanobe. 180-186 [doi]
- Automatic Generation of Fill-in-the-Blank Programming ProblemsKenta Terada, Yutaka Watanobe. 187-193 [doi]
- Convolutional Neural Network for Classification of Source CodesHiroki Ohashi, Yutaka Watanobe. 194-200 [doi]
- Design of Knowledge Templates and Multi-View Symbols for Experiential LearningTakayuki Hoshino, Rentaro Yoshioka. 201-208 [doi]
- A Traffic-Robust Routing Algorithm for Network-on-Chip SystemsSiying Xu, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe. 209-216 [doi]
- Fault Detection and Localization for Network-on-Chips in Mixed-Criticality SystemsAdele Maleki, Hamidreza Ahmadian, Roman Obermaisser. 217-222 [doi]
- An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICsKhanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran. 223-228 [doi]
- A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-ChipYaoying Luo, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe. 229-235 [doi]
- Integrating Intra-and Intercellular Simulation of a 2D HL-1 Cardiac Model Based on Embedded GPUsBaohua Liu, Wenfeng Shen, Xin Zhu, Xingyu Wangchen. 236-240 [doi]
- Exploiting Model-Level Parallelism in Recurrent Neural Network AcceleratorsLu Peng, Wentao Shi, Jian Zhang, Samuel Irving. 241-248 [doi]
- Towards an Efficient Hardware Architecture for Odd-Even Based Merge SorterElsayed A. Elsayed, Kenji Kise. 249-256 [doi]
- Energy and Performance Analysis of STTRAM Caches for Mobile ApplicationsKyle Kuan, Tosiron Adegbija. 257-264 [doi]
- Designing Application-Specific Heterogeneous Architectures from Performance ModelsThanh Cong, François Charot. 265-272 [doi]
- Efficient Search-Space Encoding for System-Level Design Space Exploration of Embedded SystemsValentina Richthammer, Michael Glaß. 273-280 [doi]
- A Cloud Based Super-Optimization Method to Parallelize the Sequential Code's Nested LoopsAmin Majd, Mohammad Loni, Golnaz Sahebi, Masoud Daneshtalab, Elena Troubitsyna. 281-287 [doi]
- Real-Time Implementation of Time-Space Continuous Dynamic Programming for Air-Drawn Character Recognition Using GPUsAki Nakamura, Yuichi Okuyama, Ryuichi Oka. 288-294 [doi]
- Graph Transformations and Derivation of Scheduling Constraints Applied to the Mapping of Real-Time Distributed ApplicationsStéphane Louise. 295-303 [doi]
- MITRACA: A Next-Gen Heterogeneous ArchitectureRiadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku. 304-311 [doi]
- A Preliminary Evaluation of Building Block Computing SystemsSayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki. 312-319 [doi]
- Enhanced ID Authentication Scheme Using FPGA-Based Ring Oscillator PUFVan-Toan Tran, Quang-Kien Trinh, Van-Phuc Hoang. 320-327 [doi]
- A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA SystemKeita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano. 328-333 [doi]
- Data-Driven Scenario-Based Application Mapping for Heterogeneous Many-Core SystemsJan Spieck, Stefan Wildermann, Tobias Schwarzer, Jürgen Teich, Michael Glaß. 334-341 [doi]
- Real-Time Attitude Estimation of Sigma-Point Kalman Filter via Matrix Operation AcceleratorZeyang Dai, Lei Jing. 342-346 [doi]
- Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded SystemsManuel Strobel, Martin Radetzki. 347-353 [doi]
- A Real-Time Fault-Tolerant and Power-Efficient Multicore System on ChipAlexander M. Gruzlikov, Nikolai V. Kolesov, Dmitrii Kostygov, Marina V. Tolmacheva. 354-361 [doi]
- Statistical Analysis for Shared Resources Effects with Multi-Core Real-Time SystemsJulien Durand, Youcef Bouchebaba, Luca Santinelli. 362-371 [doi]
- Lightweight Semantics-Preserving Communication for Real-Time Automotive SoftwareEugene Yip, Erjola Lalo, Gerald Lüttgen, Andreas Sailer. 372-379 [doi]