Abstract is missing.
- System modeling and verification with UCLIDRandal E. Bryant. 3-4 [doi]
- Verification of SpecC using predicate abstractionHimanshu Jain, Daniel Kroening, Edmund M. Clarke. 7-16 [doi]
- Bounded model checking of infinite state systems: exploiting the automata hierarchyTobias Schüle, Klaus Schneider. 17-26 [doi]
- Check and simulate: a case for incorporating model checking in network simulationAhmed Sobeih, Mahesh Viswanathan, Jennifer C. Hou. 27-36 [doi]
- Curing schizophrenia by program rewriting in EsterelOlivier Tardieu, Robert de Simone. 39-48 [doi]
- Synchronous extensions to operation centric hardware description languagesGrace Nordin, James C. Hoe. 49-56 [doi]
- PROBMELA: a modeling language for communicating probabilistic processesChristel Baier, Frank Ciesinski, Marcus Größer. 57-66 [doi]
- Bluespec System Verilog: efficient, correct RTL from high level specificationsRishiyur S. Nikhil. 69-70 [doi]
- Using invariants to optimize formal specifications before code synthesisRalph D. Jeffords, Elizabeth I. Leonard. 73-82 [doi]
- Efficient code synthesis from synchronous dataflow graphsDag Björklund. 83-92 [doi]
- Designing a reorder buffer in BluespecNirav Dave. 93-102 [doi]
- The battle of accountable voting systemsDavid L. Dill. 105 [doi]
- Static priority scheduling of event triggered real time embedded systemsCagkan Erbas, Selin C. Erbas, Andy D. Pimentel. 109-118 [doi]
- The BUSpec platform for automated generation of verification aids for standard bus protocolsBhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti. 119-128 [doi]
- Formal verification of pipelined processors with precise exceptionsKrishnamani Kalyanasundaram, R. K. Shyamasundar. 129-139 [doi]
- Is formal being squeezed out of functional verification?Brian Bailey. 143 [doi]
- Formal methods and software reliabilityGerard J. Holzmann. 145-146 [doi]
- Formal verification as a technology transfer problemRobert P. Kurshan. 147-150 [doi]
- Static driver verifier, a formal verification tool for Windows device driversVladimir Levin. 151 [doi]
- Formal verification in Intel CPU designJohn O Leary. 152 [doi]
- Designers want proofs - but show me the moneyCarl Pixley, D. Meyers, S. McMaster, A. Chittor. 153-154 [doi]
- Panel: given that hardware verification has been an uphill battle, what is the future of software verification?Sandeep K. Shukla, Tevfik Bultan, Constance L. Heitmeyer. 157-158 [doi]
- Classes and subclasses in actor-oriented designEdward A. Lee, Stephen Neuendorffer. 161-168 [doi]
- Checkers for SystemC designsDaniel Große, Rolf Drechsler. 171-178 [doi]
- Hierarchical reconfiguration of dataflow modelsStephen Neuendorffer, Edward A. Lee. 179-188 [doi]
- The ephemeral history register: flexible scheduling for rule-based designsDaniel L. Rosenband. 189-198 [doi]
- Automated, compositional and iterative deadlock detectionSagar Chaki, Edmund M. Clarke, Joël Ouaknine, Natasha Sharygina. 201-210 [doi]
- Compositional verification for secure loading of smart card appletsChristoph Sprenger, Dilian Gurov, Marieke Huisman. 211-222 [doi]
- A framework for heterogeneous formal modeling and compositional verification of avionics systemsYamine Aït Ameur, Remi Delmas, Virginie Wiels. 223-232 [doi]