Abstract is missing.
- A Framework for Formal Verification of DRAM ControllersLukas Steiner, Chirag Sudarshan, Matthias Jung 0001, Dominik Stoffel, Norbert Wehn. [doi]
- Exploiting Data Source Distribution to Enhance NVM ReliabilityAmit Berman. [doi]
- Toward Classification of Phase Change Memory and 3D NAND Flash SSDs Using Power-based Side-channel Analysis in the Time-domainJennie Hill, Justin A. Blanco, James Shey, Ryan N. Rakvic, Owens Walker. [doi]
- In-memory Bulk Bitwise Logic Operation for Multi-level Cell Non-volatile MemoriesSayed Ahmad Salehi. [doi]
- Evaluating HPC Kernels for Processing in MemoryKazi Asifuzzaman, Mohammad Alaul Haque Monil, Frank Liu 0001, Jeffrey S. Vetter. [doi]
- A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM DevicesKaustav M. Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee. [doi]
- Cronus: Computer Vision-based Machine Intelligent Hybrid Memory ManagementThaleia Dimitra Doudali, Ada Gavrilovska. [doi]
- Dynamic Page Policy Using Perceptron LearningMuhammad M. Rafique, Zhichun Zhu. [doi]
- Unveiling the Real Performance of LPDDR5 MemoriesLukas Steiner, Matthias Jung 0001, Michael Huonker, Norbert Wehn. [doi]
- Using Many Small 1T1C Memory Arrays in a Large and Dense Multicore ProcessorGunnar Carlstedt, Mats Rimborg. [doi]
- FPGA-accelerated simulation of variable latency memory systemsHüsrev Cilasun, Chris Macaraeg, Ivy Bo Peng, Abhik Sarkar, Maya B. Gokhale. [doi]
- Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows SmartlySamiksha Verma, Shirshendu Das, Vipul Bondre. [doi]