Abstract is missing.
- Microarchitecture and Design Challenges for Gigascale IntegrationShekhar Y. Borkar. 3
- Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline CommunicationPeter G. Sassone, D. Scott Wills. 7-17 [doi]
- Dataflow Mini-Graphs: Amplifying Superscalar Capacity and BandwidthAnne Bracy, Prashant Prahlad, Amir Roth. 18-29 [doi]
- Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set CustomizationNathan Clark, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke, Krisztián Flautner. 30-40 [doi]
- MicroLib: A Case for the Quantitative Comparison of Micro-Architecture MechanismsDaniel Gracia Pérez, Gilles Mouchard, Olivier Temam. 43-54 [doi]
- Automatic Synthesis of High-Speed Processor SimulatorsMartin Burtscher, Ilya Ganusov. 55-66 [doi]
- Thermal Modeling, Characterization and Management of On-Chip NetworksLi Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha. 67-78 [doi]
- Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic InstrumentationHarish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi. 81-92 [doi]
- The Fuzzy Correlation between Code and Performance PredictabilityMurali Annavaram, Ryan Rakvic, Marzia Polito, Jean-Yves Bouguet, Richard A. Hankins, Bob Davies. 93-104 [doi]
- Whole Execution TracesXiangyu Zhang, Rajiv Gupta. 105-116 [doi]
- Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and RecoveryDavid N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt. 119-128 [doi]
- Control Flow Optimization Via Dynamic Reconvergence PredictionJamison D. Collins, Dean M. Tullsen, Hong Wang 0003. 129-140 [doi]
- Single-Chip Multiprocessors: The Next Wave of Computer Architecture InnovationGurindar S. Sohi. 143
- A Case for Clumsy Packet ProcessorsArindam Mallik, Gokhan Memik. 147-156 [doi]
- Dynamically Trading Frequency for Complexity in a GALS MicroprocessorSteven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott. 157-168 [doi]
- Dynamically Controlled Resource Allocation in SMT ProcessorsFrancisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández. 171-182 [doi]
- Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading HierarchyEric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder. 183-194 [doi]
- Conjoined-Core Chip MultiprocessingRakesh Kumar, Norman P. Jouppi, Dean M. Tullsen. 195-206 [doi]
- Hardware and Binary Modification Support for Code Pointer Protection From Buffer OverflowNathan Tuck, Brad Calder, George Varghese. 209-220 [doi]
- Minos: Control Data Attack Prevention Orthogonal to Memory ModelJedidiah R. Crandall, Frederic T. Chong. 221-232 [doi]
- A Hardware-Software Platform for Intrusion PreventionMilenko Drinic, Darko Kirovski. 233-242 [doi]
- RIFLE: An Architectural Framework for User-Centric Information-Flow SecurityNeil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, David I. August. 243-254 [doi]
- Efficient Resource Sharing in Concurrent Error Detecting Superscalar MicroarchitecturesJared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi. 257-268 [doi]
- AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based InvariantsPin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas. 269-280 [doi]
- Optimal Superblock Scheduling Using EnumerationGhassan Shobaki, Kent D. Wilken. 283-293 [doi]
- Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux SystemsGerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel M. Lavery, Yong-Fong Lee, Wei Li. 294-303 [doi]
- Register Packing: Exploiting Narrow-Width Operands for Reducing Register File PressureOguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev. 304-315 [doi]
- Managing Wire Delay in Large Chip-Multiprocessor CachesBradford M. Beckmann, David A. Wood. 319-330 [doi]
- Cache Refill/Access Decoupling for Vector MachinesChristopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic. 331-342 [doi]
- Adaptive History-Based Memory SchedulersIbrahim Hur, Calvin Lin. 343-354 [doi]
- Memory Controller Optimizations for Web ServersScott Rixner. 355-366 [doi]