Abstract is missing.
- Message from the General Chairs [doi]
- Message from the Program Co-Chairs [doi]
- The Cell Processor ArchitectureJames A. Kahle. 3 [doi]
- How to Fake 1000 RegistersDavid W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt. 7-18 [doi]
- Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindowsStephen Hines, Gary S. Tyson, David B. Whalley. 19-29 [doi]
- Efficient Use of Invisible Registers in Thumb CodeArvind Krishnaswamy, Rajiv Gupta. 30-42 [doi]
- Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated ExecutionHyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt. 43-54 [doi]
- A Criticality Analysis of Clustering in Superscalar ProcessorsPierre Salverda, Craig B. Zilles. 55-66 [doi]
- Incremental Commit Groups for Non-Atomic Trace ProcessingMatt T. Yourst, Kanad Ghose. 67-80 [doi]
- Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of GranularitiesTaku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita. 81-92 [doi]
- Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP ProcessorJiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham. 93-104 [doi]
- Automatic Thread Extraction with Decoupled Software PipeliningGuilherme Ottoni, Ram Rangan, Adam Stoler, David I. August. 105-118 [doi]
- Exploiting Vector Parallelism in Software Pipelined LoopsSamuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe. 119-129 [doi]
- Continuous Path and Edge ProfilingMichael D. Bond, Kathryn S. McKinley. 130-140 [doi]
- Improving Region Selection in Dynamic Optimization SystemsDavid Hiniker, Kim M. Hazelwood, Michael D. Smith. 141-154 [doi]
- The Future Evolution of High-Performance MicroprocessorsNorman P. Jouppi. 155 [doi]
- Scalable Store-Load Forwarding via Store Queue Index PredictionTingting Sha, Milo M. K. Martin, Amir Roth. 159-170 [doi]
- Address-Indexed Memory Disambiguation and Store-to-Load ForwardingSam S. Stone, Kevin M. Woley, Matthew I. Frank. 171-182 [doi]
- Store Memory-Level Parallelism Optimizations for Commercial ApplicationsYuan Chou, Lawrence Spracklen, Santosh G. Abraham. 183-196 [doi]
- A Mechanism for Online Diagnosis of Hard Faults in MicroprocessorsFred A. Bower, Daniel J. Sorin, Sule Ozev. 197-208 [doi]
- uComplexity: Estimating Processor Design EffortCyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau. 209-218 [doi]
- Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis SystemKevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke. 219-232 [doi]
- Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation PatternsOnur Mutlu, Hyesoon Kim, Yale N. Patt. 233-244 [doi]
- Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip MultiprocessorsMeyrem Kirman, Nevin Kirman, José F. Martínez. 245-256 [doi]
- ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward SlicingSmruti R. Sarangi, Wei Liu, Yuanyuan Zhou. 257-270 [doi]
- A Dynamic Compilation Framework for Controlling Microprocessor Energy and PerformanceQiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks. 271-282 [doi]
- Thermal Management of On-Chip Caches Through Power Density MinimizationJa Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail. 283-293 [doi]
- Balancing Resource Utilization to Mitigate Power Density in Processor PipelinesMichael D. Powell, Ethan Schuchman, T. N. Vijaykumar. 294-304 [doi]
- A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and ComputationTzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross. 305-318 [doi]
- Flea-flicker Multipass Pipelining: An Alternative to the High-Power Out-of-Order OffenseRonald D. Barnes, Shane Ryoo, Wen-mei W. Hwu. 319-330 [doi]
- The TM3270 Media-ProcessorJan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen. 331-342 [doi]
- Stream Programming on General-Purpose ProcessorsJayanth Gummaraju, Mendel Rosenblum. 343-354 [doi]
- Shader Performance Analysis on a Modern GPU ArchitectureVictor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa. 355-364 [doi]