Abstract is missing.
- Dynamic redundancy allocation for reliable and high-performance nanocomputingShuo Wang, Lei Wang 0003, Faquir C. Jain. 1-6 [doi]
- Design-space exploration of fault-tolerant building blocks for large-scale quantum computingTzvetan S. Metodi, Andrew W. Cross, Darshan D. Thaker, Isaac L. Chuang, Frederic T. Chong. 7-14 [doi]
- A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functionsAshish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky. 15-20 [doi]
- Analysis of defect tolerance in molecular electronics using information-theoretic measuresJianwei Dai, Lei Wang 0003, Faquir C. Jain. 21-26 [doi]
- Design automation for hybrid CMOS-nonoelectronics crossbarsKyosun Kim, Ramesh Karri, Alex Orailoglu. 27-32 [doi]
- A fast, numerical circuit-level model of carbon nanotube transistorTom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi. 33-37 [doi]
- A ballistic nanoelectronic device simulatorDennis Huo, Qiaoyan Yu, Paul Ampadu. 38-45 [doi]
- Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulationsDrew C. Ness, Christian J. Hescott, David J. Lilja. 46-53 [doi]
- A shift-register-based QCA memory architectureBaris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo. 54-61 [doi]
- Thermally-induced soft errors in nanoscale CMOS circuitsHua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar. 62-69 [doi]
- Robust self-assembly of interconnects by parallel DNA growthMasoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi. 70-76 [doi]
- Design of high-yield defect-tolerant self-assembled nanoscale memoriesGirish Venkatasubramanian, P. Oscar Boykin, Renato J. O. Figueiredo. 77-84 [doi]
- A pageable, defect-tolerant nanoscale memory systemSusmit Biswas, Frederic T. Chong, Tzvetan S. Metodi, Ryan Kastner. 85-92 [doi]
- Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computingZhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen 0002. 93-100 [doi]
- Combining 2-level logic families in grid-based nanoscale fabricsTeng Wang, Pritish Narayanan, Csaba Andras Moritz. 101-108 [doi]
- Prospects for the development of digital CMOL circuitsDmitri B. Strukov, Konstantin K. Likharev. 109-116 [doi]
- Crossbar latch-based combinational and sequential logic for nano FPGATamer Mohamed, Graham A. Jullien, Wael M. Badawy. 117-122 [doi]
- Clocking nanocircuits for nanocomputers and other nanoelectronic systemsShamik Das, Matthew F. Bauwens. 123-128 [doi]